[PATCH] D101489: [InstCombine] improve demanded bits analysis of left-shifted operand

[Sanjay Patel via Phabricator via llvm-commits]

spatel created this revision.
spatel added reviewers: craig.topper, lebedev.ri, nikic, RKSimon.
Herald added subscribers: hiraditya, mcrosier.
spatel requested review of this revision.
Herald added a project: LLVM.

If we don't demand high bits, then we also don't care about those high bits of a left-shift operand regardless of shift amount.
I noticed the sext/trunc pattern in a motivating example.
It seems like there should be a low-bits with right-shift sibling, but I haven't looked at that yet.

https://alive2.llvm.org/ce/z/JuS6jc
https://rise4fun.com/Alive/Trm  (not sure how to use 'width' with Alive1)
https://alive2.llvm.org/ce/z/gRadbF


https://reviews.llvm.org/D101489

Files:
  llvm/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp
  llvm/test/Transforms/InstCombine/rotate.ll
  llvm/test/Transforms/InstCombine/shl-demand.ll

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