[PATCH] D101470: [XCOFF][AIX] Peephole optimization in TocData transformation
Sidharth Baveja via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Wed Apr 28 09:28:49 PDT 2021
sidbav created this revision.
sidbav added reviewers: sfertile, hubert.reinterpretcast, daltenty, jasonliu.
Herald added subscribers: kbarton, hiraditya, nemanjai.
sidbav requested review of this revision.
Herald added a project: LLVM.
Herald added a subscriber: llvm-commits.
This patch is a followup to D101178 <https://reviews.llvm.org/D101178>.
In the patch, we enable peephole optimization (when possible) for the toc data transformation.
For example, with this patch would allow for the following assembly code:
la 4, i[TD](2)
stw 3, 0(4)
to be transformed to the following instead:
stw 3, i[TD](2)
This patch can only be merged in after D101178 <https://reviews.llvm.org/D101178> has been accepted and merged into LLVM.
Repository:
rG LLVM Github Monorepo
https://reviews.llvm.org/D101470
Files:
llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
llvm/lib/Target/PowerPC/PPCMCInstLower.cpp
llvm/test/CodeGen/PowerPC/toc-data.ll
Index: llvm/test/CodeGen/PowerPC/toc-data.ll
===================================================================
--- llvm/test/CodeGen/PowerPC/toc-data.ll
+++ llvm/test/CodeGen/PowerPC/toc-data.ll
@@ -14,12 +14,11 @@
ret void
}
; CHECK: name: write_int
-; CHECK: %[[SCRATCH:[0-9]+]]:gprc_and_gprc_nor0 = ADDItoc @i, $r2
-; CHECK-NEXT: STW %{{[0-9]+}}, 0, killed %[[SCRATCH]] :: (store 4 into @i)
+; CHECK: %[[SCRATCH:[0-9]+]]:gprc = COPY $r3
+; CHECK-NEXT: STW %{{[0-9]+}}, @i, $r2 :: (store 4 into @i)
; TEST: .write_int:
-; TEST: la 4, i[TD](2)
-; TEST-NEXT: stw 3, 0(4)
+; TEST: stw 3, i[TD](2)
define dso_local i64 @read_ll() {
entry:
@@ -40,12 +39,10 @@
ret float %0
}
; CHECK: name: read_float
-; CHECK: %[[SCRATCH:[0-9]+]]:gprc_and_gprc_nor0 = ADDItoc @f, $r2
-; CHECK: %{{[0-9]+}}:f4rc = LFS 0, killed %[[SCRATCH]] :: (dereferenceable load 4 from @f)
+; CHECK: %{{[0-9]+}}:f4rc = LFS @f, $r2 :: (dereferenceable load 4 from @f)
; TEST: .read_float:
-; TEST: la 3, f[TD](2)
-; TEST-NEXT: lfs 1, 0(3)
+; TEST: lfs 1, f[TD](2)
define dso_local void @write_double(double %in) {
entry:
@@ -76,7 +73,8 @@
ret i32 %0
}
; CHECK: name: read_i32_linkage
-; CHECK: LWZtoc @ilocal, $r2 :: (load 4 from got)
+; CHECK: %[[SCRATCH:[0-9]+]]:gprc_and_gprc_nor0 = LWZtoc @ilocal, $r2 :: (load 4 from got)
+; CHECK-NEXT: LWZ 0, killed %[[SCRATCH]] :: (dereferenceable load 4 from @ilocal)
; TEST: .read_i32_linkage:
; TEST: lwz 3, L..C2(2)
Index: llvm/lib/Target/PowerPC/PPCMCInstLower.cpp
===================================================================
--- llvm/lib/Target/PowerPC/PPCMCInstLower.cpp
+++ llvm/lib/Target/PowerPC/PPCMCInstLower.cpp
@@ -42,6 +42,11 @@
Mangler::getNameWithPrefix(Name, MO.getSymbolName(), DL);
} else {
const GlobalValue *GV = MO.getGlobal();
+
+ if (const GlobalVariable *GVar = dyn_cast<GlobalVariable>(GV))
+ if (GVar->hasAttribute("toc-data"))
+ return AP.getSymbol(GV);
+
TM.getNameWithPrefix(Name, GV, Mang);
}
Index: llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
===================================================================
--- llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
+++ llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
@@ -7092,6 +7092,7 @@
Flags = PPCII::MO_TLSLD_LO;
break;
case PPC::ADDItocL:
+ case PPC::ADDItoc:
Flags = PPCII::MO_TOC_LO;
break;
}
@@ -7189,9 +7190,18 @@
}
if (FirstOp == 1) // Store
- (void)CurDAG->UpdateNodeOperands(N, N->getOperand(0), ImmOpnd,
- Base.getOperand(0), N->getOperand(3));
+ if (Base.getMachineOpcode() == PPC::ADDItoc)
+ (void)CurDAG->UpdateNodeOperands(N, N->getOperand(0),
+ Base.getOperand(0), Base.getOperand(1),
+ N->getOperand(3));
+ else
+ (void)CurDAG->UpdateNodeOperands(N, N->getOperand(0), ImmOpnd,
+ Base.getOperand(0), N->getOperand(3));
else // Load
+ if (Base.getMachineOpcode() == PPC::ADDItoc)
+ (void)CurDAG->UpdateNodeOperands(N, Base.getOperand(0),
+ Base.getOperand(1), N->getOperand(2));
+ else
(void)CurDAG->UpdateNodeOperands(N, ImmOpnd, Base.getOperand(0),
N->getOperand(2));
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