[PATCH] D101062: [AArch64][SVE] Better utilisation of immediate forms for bitwise/arith intrinsics
Bradley Smith via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Wed Apr 28 03:38:58 PDT 2021
bsmith updated this revision to Diff 341130.
bsmith marked an inline comment as done.
bsmith added a comment.
- Use all active predicate logic in convertMergedOpToPredOp for arith nodes
- Remove intrinsic patterns for arith nodes since the above will convert them to ISD nodes, which already have patterns
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D101062/new/
https://reviews.llvm.org/D101062
Files:
llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
llvm/lib/Target/AArch64/SVEInstrFormats.td
llvm/test/CodeGen/AArch64/sve-intrinsics-int-arith-imm.ll
llvm/test/CodeGen/AArch64/sve-intrinsics-logical-imm.ll
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