[PATCH] D101369: [AArch64][SVE] Fold insert(zero, extract(X, 0), 0) -> X, when X is known to zero lanes 1-N

[David Sherwood via Phabricator via llvm-commits]

david-arm added inline comments.


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Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:15894
+// result contains data, with all bits in other lanes set to zero.
+static bool isLanes1toNKnownZero(SDValue Op) {
+  switch (Op.getOpcode()) {
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paulwalker-arm wrote:
> david-arm wrote:
> > Sorry to chip in here as I realise I'm not a reviewer. :) However, the ANDV instruction has a scalar SIMD&FP register for it's result, so it doesn't feel right to say all the other lanes >0 in the equivalent SVE register are zero. I'd have expected something more like isOnlyFirstLaneDefined? I understand you named this function because currently it's only called from performInsertVectorEltCombine where the insert vector is a null splat, but other users may call it elsewhere in future and it feels a bit dangerous to give it a misleading name that's all.
> This is not true @david-arm .  The SVE reduction nodes are defined to return a vector result to match the instructions behaviour of modifying all bits of their destination Z register.  You can see this in LowerReductionToSVE where after the reduction we extract the scalar required to match the definition of the common `VECREDUCE` nodes.  This patch is one of the reasons we do this so the explicit behaviour is captured and thus can be taken advantage of.
Ah ok, fair enough. I was just looking at the actual ANDV instruction in the developer manual that's all, whereas from what you're saying we've defined ANDV_PRED to zero all lanes > 0. Sorry for the confusion!


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  https://reviews.llvm.org/D101369/new/

https://reviews.llvm.org/D101369