[PATCH] D101369: [AArch64][SVE] Fold insert(zero, extract(X, 0), 0) -> X, when X is known to zero lanes 1-N

[Dave Green via Phabricator via llvm-commits]

dmgreen added a comment.

The documentation for the nodes you are using the implicit zeroing of say "// Only the lower result lane is defined." Should that be changed to explain that all non-zero lanes are zero?



================
Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:15919
+// or a constant positive 0 floating point value.
+static bool isNullSplat(SDValue Splat) {
+  if (Splat.getOpcode() != ISD::SPLAT_VECTOR)
----------------
Can this use isConstantSplatVectorAllZeros?


================
Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:16047-16050
+    SDValue Res = performInsertVectorEltCombine(N, DAG);
+    if (Res == SDValue())
+      return performPostLD1Combine(N, DCI, true);
+    return Res;
----------------
I would create a function for this, to keep PerformDAGCombine straight forward.
It is common to do:
```
if (SDValue Res = performInsertVectorEltCombine(N, DAG))
  return Res
return performPostLD1Combine(N, DCI, true);
```


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  https://reviews.llvm.org/D101369/new/

https://reviews.llvm.org/D101369