[PATCH] D101369: [AArch64][SVE] Fold insert(zero, extract(X, 0), 0) -> X, when X is known to zero lanes 1-N

[Peter Waller via Phabricator via llvm-commits]

peterwaller-arm added inline comments.


================
Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:16048
+    SDValue Res = performInsertVectorEltCombine(N, DAG);
+    if (Res == SDValue())
+      return performPostLD1Combine(N, DCI, true);
----------------
peterwaller-arm wrote:
> Nit: indent.
> 
> Also suggestion: `if (Res != SDValue()) return Res;`, that way the code can be extended to handle other combines that come in the future with minimal further changes.
Erratum: not sure what I was seeing with the whitespace. I think I misread phabricator's diff whitespace hints here.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D101369/new/

https://reviews.llvm.org/D101369