[PATCH] D101246: [RISCV] Select 5 bit immediate for VSETIVLI during isel rather than peepholing in the custom inserter.

Zakk Chen via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Tue Apr 27 00:42:06 PDT 2021

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khchen accepted this revision.
khchen added a comment.
This revision is now accepted and ready to land.

Thanks for clarification, LGTM.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D101246/new/

https://reviews.llvm.org/D101246

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