[PATCH] D101246: [RISCV] Select 5 bit immediate for VSETIVLI during isel rather than peepholing in the custom inserter.

[Craig Topper via Phabricator via llvm-commits]

craig.topper added a comment.

In D101246#2717226 <https://reviews.llvm.org/D101246#2717226>, @khchen wrote:

> Select the immediate during isel does make sense to me, but unfortunately there are some cases have a slower result.
> Do you know is there any cases which have better instruction order and reduce register spilling when apply the new scheme?
> I'm just afraid of the new one would be always generate the slower instruction order.

I think the extra spilling cases are gone now. Those were LMUL=8 cases on RV32 where we used 2 vector register groups to splat a 64 bit element. This left 2 register groups to use for other things. It looks like we're also using a vlmax splat when we have a fixed length vector which causes an extra vsetvli that acts as a scheduling barrier. Some of this should be improved now because we're using a stack store instead of tying up 2 vector registers. We're at least not spilling anymore.


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https://reviews.llvm.org/D101246