[llvm] 3064a63 - [RISCV] Remove GetVRegNoV0 from the output register class of masked compare pseudo instructions.
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Fri Apr 23 09:40:27 PDT 2021
Author: Craig Topper
Date: 2021-04-23T09:33:29-07:00
New Revision: 3064a63b2b330a229d0b236472549dc832ce1701
URL: https://github.com/llvm/llvm-project/commit/3064a63b2b330a229d0b236472549dc832ce1701
DIFF: https://github.com/llvm/llvm-project/commit/3064a63b2b330a229d0b236472549dc832ce1701.diff
LOG: [RISCV] Remove GetVRegNoV0 from the output register class of masked compare pseudo instructions.
Theses instructions are allowed to write v0 when they are masked.
We'll still never use v0 because of the earlyclobber constraint so
this doesn't really help anything. It just makes the definitions
correct.
While I was there remove an unused multiclass I noticed.
Reviewed By: HsiangKai
Differential Revision: https://reviews.llvm.org/D101118
Added:
Modified:
llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
llvm/test/CodeGen/RISCV/rvv/vmseq-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vmsge-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vmsgeu-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vmsgt-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vmsgtu-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vmsle-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vmsleu-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vmslt-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vmsltu-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vmsne-rv32.ll
Removed:
################################################################################
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td b/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
index 1f0975a81442..a38bb0c14891 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
@@ -884,23 +884,6 @@ class VPseudoMaskUnarySOutMask:
let BaseInstr = !cast<Instruction>(PseudoToVInst<NAME>.VInst);
}
-// Masked mask operation have no $rd=$merge constraints
-class VPseudoUnaryMOutMask:
- Pseudo<(outs VR:$rd),
- (ins VR:$merge, VR:$rs1, VMaskOp:$vm, GPR:$vl, ixlenimm:$sew), []>,
- RISCVVPseudo {
- let mayLoad = 0;
- let mayStore = 0;
- let hasSideEffects = 0;
- let usesCustomInserter = 1;
- let Constraints = "$rd = $merge";
- let Uses = [VL, VTYPE];
- let HasVLOp = 1;
- let HasSEWOp = 1;
- let HasMergeOp = 1;
- let BaseInstr = !cast<Instruction>(PseudoToVInst<NAME>.VInst);
-}
-
// Mask can be V0~V31
class VPseudoUnaryAnyMask<VReg RetClass,
VReg Op1Class> :
@@ -995,6 +978,28 @@ class VPseudoBinaryMask<VReg RetClass,
let BaseInstr = !cast<Instruction>(PseudoToVInst<NAME>.VInst);
}
+// Like VPseudoBinaryMask, but output can be V0.
+class VPseudoBinaryMOutMask<VReg RetClass,
+ RegisterClass Op1Class,
+ DAGOperand Op2Class,
+ string Constraint> :
+ Pseudo<(outs RetClass:$rd),
+ (ins RetClass:$merge,
+ Op1Class:$rs2, Op2Class:$rs1,
+ VMaskOp:$vm, GPR:$vl, ixlenimm:$sew), []>,
+ RISCVVPseudo {
+ let mayLoad = 0;
+ let mayStore = 0;
+ let hasSideEffects = 0;
+ let usesCustomInserter = 1;
+ let Constraints = Join<[Constraint, "$rd = $merge"], ",">.ret;
+ let Uses = [VL, VTYPE];
+ let HasVLOp = 1;
+ let HasSEWOp = 1;
+ let HasMergeOp = 1;
+ let BaseInstr = !cast<Instruction>(PseudoToVInst<NAME>.VInst);
+}
+
class VPseudoBinaryCarryIn<VReg RetClass,
VReg Op1Class,
DAGOperand Op2Class,
@@ -1507,6 +1512,19 @@ multiclass VPseudoBinary<VReg RetClass,
}
}
+multiclass VPseudoBinaryM<VReg RetClass,
+ VReg Op1Class,
+ DAGOperand Op2Class,
+ LMULInfo MInfo,
+ string Constraint = ""> {
+ let VLMul = MInfo.value in {
+ def "_" # MInfo.MX : VPseudoBinaryNoMask<RetClass, Op1Class, Op2Class,
+ Constraint>;
+ def "_" # MInfo.MX # "_MASK" : VPseudoBinaryMOutMask<RetClass, Op1Class,
+ Op2Class, Constraint>;
+ }
+}
+
multiclass VPseudoBinaryEmul<VReg RetClass,
VReg Op1Class,
DAGOperand Op2Class,
@@ -1740,25 +1758,25 @@ multiclass PseudoUnaryV_VF8 {
// @earlyclobber to avoid the overlap between destination and source registers.
multiclass VPseudoBinaryM_VV {
foreach m = MxList.m in
- defm _VV : VPseudoBinary<VR, m.vrclass, m.vrclass, m, "@earlyclobber $rd">;
+ defm _VV : VPseudoBinaryM<VR, m.vrclass, m.vrclass, m, "@earlyclobber $rd">;
}
multiclass VPseudoBinaryM_VX {
foreach m = MxList.m in
defm "_VX" :
- VPseudoBinary<VR, m.vrclass, GPR, m, "@earlyclobber $rd">;
+ VPseudoBinaryM<VR, m.vrclass, GPR, m, "@earlyclobber $rd">;
}
multiclass VPseudoBinaryM_VF {
foreach m = MxList.m in
foreach f = FPList.fpinfo in
defm "_V" # f.FX :
- VPseudoBinary<VR, m.vrclass, f.fprclass, m, "@earlyclobber $rd">;
+ VPseudoBinaryM<VR, m.vrclass, f.fprclass, m, "@earlyclobber $rd">;
}
multiclass VPseudoBinaryM_VI {
foreach m = MxList.m in
- defm _VI : VPseudoBinary<VR, m.vrclass, simm5, m, "@earlyclobber $rd">;
+ defm _VI : VPseudoBinaryM<VR, m.vrclass, simm5, m, "@earlyclobber $rd">;
}
multiclass VPseudoBinaryV_VV_VX_VI<Operand ImmType = simm5, string Constraint = ""> {
diff --git a/llvm/test/CodeGen/RISCV/rvv/vmseq-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vmseq-rv32.ll
index cf9d68ef2a56..5e1f4d1e8b14 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vmseq-rv32.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vmseq-rv32.ll
@@ -1683,12 +1683,12 @@ define <vscale x 1 x i1> @intrinsic_vmseq_mask_vx_nxv1i64_i64(<vscale x 1 x i1>
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli a0, a2, e64,m1,ta,mu
; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v25, (a0), zero
-; CHECK-NEXT: vmv1r.v v26, v0
+; CHECK-NEXT: vlse64.v v26, (a0), zero
+; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli a0, a2, e64,m1,tu,mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmseq.vv v26, v8, v25, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmseq.vv v25, v8, v26, v0.t
+; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: jalr zero, 0(ra)
entry:
diff --git a/llvm/test/CodeGen/RISCV/rvv/vmsge-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vmsge-rv32.ll
index a5e6e5c23c38..be2e83d4a4d3 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vmsge-rv32.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vmsge-rv32.ll
@@ -1713,12 +1713,12 @@ define <vscale x 1 x i1> @intrinsic_vmsge_mask_vx_nxv1i64_i64(<vscale x 1 x i1>
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli a0, a2, e64,m1,ta,mu
; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v25, (a0), zero
-; CHECK-NEXT: vmv1r.v v26, v0
+; CHECK-NEXT: vlse64.v v26, (a0), zero
+; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli a0, a2, e64,m1,tu,mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmsle.vv v26, v25, v8, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmsle.vv v25, v26, v8, v0.t
+; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: jalr zero, 0(ra)
entry:
@@ -2761,11 +2761,11 @@ define <vscale x 1 x i1> @intrinsic_vmsge_maskedoff_mask_vx_nxv1i64_i64(<vscale
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli a0, a2, e64,m1,ta,mu
; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v25, (a0), zero
-; CHECK-NEXT: vmv1r.v v26, v0
+; CHECK-NEXT: vlse64.v v26, (a0), zero
+; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli a0, a2, e64,m1,tu,mu
-; CHECK-NEXT: vmsle.vv v26, v25, v8, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmsle.vv v25, v26, v8, v0.t
+; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: jalr zero, 0(ra)
entry:
diff --git a/llvm/test/CodeGen/RISCV/rvv/vmsgeu-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vmsgeu-rv32.ll
index 8bcd312fd4b3..c0161495f932 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vmsgeu-rv32.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vmsgeu-rv32.ll
@@ -1713,12 +1713,12 @@ define <vscale x 1 x i1> @intrinsic_vmsgeu_mask_vx_nxv1i64_i64(<vscale x 1 x i1>
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli a0, a2, e64,m1,ta,mu
; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v25, (a0), zero
-; CHECK-NEXT: vmv1r.v v26, v0
+; CHECK-NEXT: vlse64.v v26, (a0), zero
+; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli a0, a2, e64,m1,tu,mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmsleu.vv v26, v25, v8, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmsleu.vv v25, v26, v8, v0.t
+; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: jalr zero, 0(ra)
entry:
@@ -2761,11 +2761,11 @@ define <vscale x 1 x i1> @intrinsic_vmsgeu_maskedoff_mask_vx_nxv1i64_i64(<vscale
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli a0, a2, e64,m1,ta,mu
; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v25, (a0), zero
-; CHECK-NEXT: vmv1r.v v26, v0
+; CHECK-NEXT: vlse64.v v26, (a0), zero
+; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli a0, a2, e64,m1,tu,mu
-; CHECK-NEXT: vmsleu.vv v26, v25, v8, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmsleu.vv v25, v26, v8, v0.t
+; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: jalr zero, 0(ra)
entry:
diff --git a/llvm/test/CodeGen/RISCV/rvv/vmsgt-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vmsgt-rv32.ll
index 504b44e0be1c..199605b838a0 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vmsgt-rv32.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vmsgt-rv32.ll
@@ -1683,12 +1683,12 @@ define <vscale x 1 x i1> @intrinsic_vmsgt_mask_vx_nxv1i64_i64(<vscale x 1 x i1>
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli a0, a2, e64,m1,ta,mu
; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v25, (a0), zero
-; CHECK-NEXT: vmv1r.v v26, v0
+; CHECK-NEXT: vlse64.v v26, (a0), zero
+; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli a0, a2, e64,m1,tu,mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmslt.vv v26, v25, v8, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmslt.vv v25, v26, v8, v0.t
+; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: jalr zero, 0(ra)
entry:
diff --git a/llvm/test/CodeGen/RISCV/rvv/vmsgtu-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vmsgtu-rv32.ll
index 839722ce6c24..71e499b3ca39 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vmsgtu-rv32.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vmsgtu-rv32.ll
@@ -1683,12 +1683,12 @@ define <vscale x 1 x i1> @intrinsic_vmsgtu_mask_vx_nxv1i64_i64(<vscale x 1 x i1>
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli a0, a2, e64,m1,ta,mu
; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v25, (a0), zero
-; CHECK-NEXT: vmv1r.v v26, v0
+; CHECK-NEXT: vlse64.v v26, (a0), zero
+; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli a0, a2, e64,m1,tu,mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmsltu.vv v26, v25, v8, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmsltu.vv v25, v26, v8, v0.t
+; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: jalr zero, 0(ra)
entry:
diff --git a/llvm/test/CodeGen/RISCV/rvv/vmsle-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vmsle-rv32.ll
index 6a33e23b4ecc..74662ab9f89a 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vmsle-rv32.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vmsle-rv32.ll
@@ -1683,12 +1683,12 @@ define <vscale x 1 x i1> @intrinsic_vmsle_mask_vx_nxv1i64_i64(<vscale x 1 x i1>
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli a0, a2, e64,m1,ta,mu
; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v25, (a0), zero
-; CHECK-NEXT: vmv1r.v v26, v0
+; CHECK-NEXT: vlse64.v v26, (a0), zero
+; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli a0, a2, e64,m1,tu,mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmsle.vv v26, v8, v25, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmsle.vv v25, v8, v26, v0.t
+; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: jalr zero, 0(ra)
entry:
diff --git a/llvm/test/CodeGen/RISCV/rvv/vmsleu-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vmsleu-rv32.ll
index 8b4879b8f515..5bf609ef07f1 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vmsleu-rv32.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vmsleu-rv32.ll
@@ -1683,12 +1683,12 @@ define <vscale x 1 x i1> @intrinsic_vmsleu_mask_vx_nxv1i64_i64(<vscale x 1 x i1>
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli a0, a2, e64,m1,ta,mu
; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v25, (a0), zero
-; CHECK-NEXT: vmv1r.v v26, v0
+; CHECK-NEXT: vlse64.v v26, (a0), zero
+; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli a0, a2, e64,m1,tu,mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmsleu.vv v26, v8, v25, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmsleu.vv v25, v8, v26, v0.t
+; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: jalr zero, 0(ra)
entry:
diff --git a/llvm/test/CodeGen/RISCV/rvv/vmslt-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vmslt-rv32.ll
index 482fe2ce8db6..8ca44d66ebeb 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vmslt-rv32.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vmslt-rv32.ll
@@ -1683,12 +1683,12 @@ define <vscale x 1 x i1> @intrinsic_vmslt_mask_vx_nxv1i64_i64(<vscale x 1 x i1>
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli a0, a2, e64,m1,ta,mu
; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v25, (a0), zero
-; CHECK-NEXT: vmv1r.v v26, v0
+; CHECK-NEXT: vlse64.v v26, (a0), zero
+; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli a0, a2, e64,m1,tu,mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmslt.vv v26, v8, v25, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmslt.vv v25, v8, v26, v0.t
+; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: jalr zero, 0(ra)
entry:
diff --git a/llvm/test/CodeGen/RISCV/rvv/vmsltu-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vmsltu-rv32.ll
index d8140beab031..3ccd474a441b 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vmsltu-rv32.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vmsltu-rv32.ll
@@ -1683,12 +1683,12 @@ define <vscale x 1 x i1> @intrinsic_vmsltu_mask_vx_nxv1i64_i64(<vscale x 1 x i1>
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli a0, a2, e64,m1,ta,mu
; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v25, (a0), zero
-; CHECK-NEXT: vmv1r.v v26, v0
+; CHECK-NEXT: vlse64.v v26, (a0), zero
+; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli a0, a2, e64,m1,tu,mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmsltu.vv v26, v8, v25, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmsltu.vv v25, v8, v26, v0.t
+; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: jalr zero, 0(ra)
entry:
diff --git a/llvm/test/CodeGen/RISCV/rvv/vmsne-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vmsne-rv32.ll
index 5389e8b11e02..b8feac3c8ce6 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vmsne-rv32.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vmsne-rv32.ll
@@ -1683,12 +1683,12 @@ define <vscale x 1 x i1> @intrinsic_vmsne_mask_vx_nxv1i64_i64(<vscale x 1 x i1>
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli a0, a2, e64,m1,ta,mu
; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v25, (a0), zero
-; CHECK-NEXT: vmv1r.v v26, v0
+; CHECK-NEXT: vlse64.v v26, (a0), zero
+; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli a0, a2, e64,m1,tu,mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmsne.vv v26, v8, v25, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmsne.vv v25, v8, v26, v0.t
+; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: jalr zero, 0(ra)
entry:
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