[llvm] fae1d31 - [RISCV] Have assembler check that the temp register is different than dest register for vmsgeu.vx pseudo.

[Craig Topper via llvm-commits]

Author: Craig Topper
Date: 2021-04-23T09:33:29-07:00
New Revision: fae1d31c09172313f96e16791e823ef4b6badc5d

URL: https://github.com/llvm/llvm-project/commit/fae1d31c09172313f96e16791e823ef4b6badc5d
DIFF: https://github.com/llvm/llvm-project/commit/fae1d31c09172313f96e16791e823ef4b6badc5d.diff

LOG: [RISCV] Have assembler check that the temp register is different than dest register for vmsgeu.vx pseudo.

Reviewed By: HsiangKai

Differential Revision: https://reviews.llvm.org/D101015

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
    llvm/test/MC/RISCV/rvv/invalid.s

Removed: 
    


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diff  --git a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
index 1130e7542a609..e96a4c0d2aed6 100644
--- a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
+++ b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
@@ -2461,6 +2461,17 @@ std::unique_ptr<RISCVOperand> RISCVAsmParser::defaultMaskRegOp() const {
 
 bool RISCVAsmParser::validateInstruction(MCInst &Inst,
                                          OperandVector &Operands) {
+  if (Inst.getOpcode() == RISCV::PseudoVMSGEU_VX_M_T ||
+      Inst.getOpcode() == RISCV::PseudoVMSGE_VX_M_T) {
+    unsigned DestReg = Inst.getOperand(0).getReg();
+    unsigned TempReg = Inst.getOperand(1).getReg();
+    if (DestReg == TempReg) {
+      SMLoc Loc = Operands.back()->getStartLoc();
+      return Error(Loc, "The temporary vector register cannot be the same as "
+                        "the destination register.");
+    }
+  }
+
   const MCInstrDesc &MCID = MII.get(Inst.getOpcode());
   unsigned Constraints =
       (MCID.TSFlags & RISCVII::ConstraintMask) >> RISCVII::ConstraintShift;

diff  --git a/llvm/test/MC/RISCV/rvv/invalid.s b/llvm/test/MC/RISCV/rvv/invalid.s
index 35a88e4aa0bef..501cbe2854e95 100644
--- a/llvm/test/MC/RISCV/rvv/invalid.s
+++ b/llvm/test/MC/RISCV/rvv/invalid.s
@@ -666,3 +666,9 @@ vmsge.vx v2, v4, a0, v0.t, v0
 
 vmsgeu.vx v2, v4, a0, v0.t, v0
 # CHECK-ERROR: invalid operand for instruction
+
+vmsge.vx v2, v4, a0, v0.t, v2
+# CHECK-ERROR: The temporary vector register cannot be the same as the destination register.
+
+vmsgeu.vx v2, v4, a0, v0.t, v2
+# CHECK-ERROR: The temporary vector register cannot be the same as the destination register.