[llvm] 2e72f6b - AArch64: support mixed-size fp <-> int conversions in GlobalISel.
Tim Northover via llvm-commits
llvm-commits at lists.llvm.org
Thu Apr 22 07:03:26 PDT 2021
Author: Tim Northover
Date: 2021-04-22T15:03:17+01:00
New Revision: 2e72f6b5d898ceb4c18325dce55d1798256682ff
URL: https://github.com/llvm/llvm-project/commit/2e72f6b5d898ceb4c18325dce55d1798256682ff
DIFF: https://github.com/llvm/llvm-project/commit/2e72f6b5d898ceb4c18325dce55d1798256682ff.diff
LOG: AArch64: support mixed-size fp <-> int conversions in GlobalISel.
Added:
Modified:
llvm/lib/Target/AArch64/AArch64InstrGISel.td
llvm/test/CodeGen/AArch64/GlobalISel/select-fp-casts.mir
llvm/utils/TableGen/GlobalISelEmitter.cpp
Removed:
################################################################################
diff --git a/llvm/lib/Target/AArch64/AArch64InstrGISel.td b/llvm/lib/Target/AArch64/AArch64InstrGISel.td
index 25656fac1d2f1..be8d8352d7f01 100644
--- a/llvm/lib/Target/AArch64/AArch64InstrGISel.td
+++ b/llvm/lib/Target/AArch64/AArch64InstrGISel.td
@@ -182,3 +182,24 @@ def : GINodeEquiv<G_EXTRACT_VECTOR_ELT, vector_extract>;
def : Pat<(f32 (fadd (vector_extract (v2f32 FPR64:$Rn), (i64 0)),
(vector_extract (v2f32 FPR64:$Rn), (i64 1)))),
(f32 (FADDPv2i32p (v2f32 FPR64:$Rn)))>;
+
+let Predicates = [HasNEON] in {
+ def : Pat<(v2f64 (sint_to_fp v2i32:$src)),
+ (SCVTFv2f64 (SSHLLv2i32_shift V64:$src, 0))>;
+ def : Pat<(v2f64 (uint_to_fp v2i32:$src)),
+ (UCVTFv2f64 (USHLLv2i32_shift V64:$src, 0))>;
+ def : Pat<(v2f32 (sint_to_fp v2i64:$src)),
+ (FCVTNv2i32 (SCVTFv2f64 V128:$src))>;
+ def : Pat<(v2f32 (uint_to_fp v2i64:$src)),
+ (FCVTNv2i32 (UCVTFv2f64 V128:$src))>;
+
+ def : Pat<(v2i64 (fp_to_sint v2f32:$src)),
+ (FCVTZSv2f64 (FCVTLv2i32 V64:$src))>;
+ def : Pat<(v2i64 (fp_to_uint v2f32:$src)),
+ (FCVTZUv2f64 (FCVTLv2i32 V64:$src))>;
+ def : Pat<(v2i32 (fp_to_sint v2f64:$src)),
+ (XTNv2i32 (FCVTZSv2f64 V128:$src))>;
+ def : Pat<(v2i32 (fp_to_uint v2f64:$src)),
+ (XTNv2i32 (FCVTZUv2f64 V128:$src))>;
+
+}
\ No newline at end of file
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-fp-casts.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-fp-casts.mir
index 4274f91dba49c..c859e42548629 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/select-fp-casts.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-fp-casts.mir
@@ -81,8 +81,8 @@ body: |
liveins: $d0
; CHECK-LABEL: name: fptrunc_v4s16_v4s32_fpr
; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
- ; CHECK: [[FCVTNv4i16:%[0-9]+]]:fpr64 = FCVTNv4i16 [[COPY]]
- ; CHECK: $d0 = COPY [[FCVTNv4i16]]
+ ; CHECK: [[FCVTNv4i16_:%[0-9]+]]:fpr64 = FCVTNv4i16 [[COPY]]
+ ; CHECK: $d0 = COPY [[FCVTNv4i16_]]
%0(<4 x s32>) = COPY $q0
%1(<4 x s16>) = G_FPTRUNC %0
$d0 = COPY %1(<4 x s16>)
@@ -102,8 +102,8 @@ body: |
liveins: $q0
; CHECK-LABEL: name: fptrunc_v2s32_v2s64_fpr
; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
- ; CHECK: [[FCVTNv2i32:%[0-9]+]]:fpr64 = FCVTNv2i32 [[COPY]]
- ; CHECK: $d0 = COPY [[FCVTNv2i32]]
+ ; CHECK: [[FCVTNv2i32_:%[0-9]+]]:fpr64 = FCVTNv2i32 [[COPY]]
+ ; CHECK: $d0 = COPY [[FCVTNv2i32_]]
%0(<2 x s64>) = COPY $q0
%1(<2 x s32>) = G_FPTRUNC %0
$d0 = COPY %1(<2 x s32>)
@@ -189,8 +189,8 @@ body: |
liveins: $d0
; CHECK-LABEL: name: fpext_v4s32_v4s16_fpr
; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
- ; CHECK: [[FCVTLv4i16:%[0-9]+]]:fpr128 = FCVTLv4i16 [[COPY]]
- ; CHECK: $q0 = COPY [[FCVTLv4i16]]
+ ; CHECK: [[FCVTLv4i16_:%[0-9]+]]:fpr128 = FCVTLv4i16 [[COPY]]
+ ; CHECK: $q0 = COPY [[FCVTLv4i16_]]
%0(<4 x s16>) = COPY $d0
%1(<4 x s32>) = G_FPEXT %0
$q0 = COPY %1(<4 x s32>)
@@ -210,8 +210,8 @@ body: |
liveins: $d0
; CHECK-LABEL: name: fpext_v2s64_v2s32_fpr
; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
- ; CHECK: [[FCVTLv2i32:%[0-9]+]]:fpr128 = FCVTLv2i32 [[COPY]]
- ; CHECK: $q0 = COPY [[FCVTLv2i32]]
+ ; CHECK: [[FCVTLv2i32_:%[0-9]+]]:fpr128 = FCVTLv2i32 [[COPY]]
+ ; CHECK: $q0 = COPY [[FCVTLv2i32_]]
%0(<2 x s32>) = COPY $d0
%1(<2 x s64>) = G_FPEXT %0
$q0 = COPY %1(<2 x s64>)
@@ -254,8 +254,8 @@ body: |
; CHECK-LABEL: name: sitofp_s32_s32_fpr_fpr
; CHECK: [[COPY:%[0-9]+]]:fpr32 = COPY $s0
- ; CHECK: [[SCVTFv1i32:%[0-9]+]]:fpr32 = SCVTFv1i32 [[COPY]]
- ; CHECK: $s0 = COPY [[SCVTFv1i32]]
+ ; CHECK: [[SCVTFv1i32_:%[0-9]+]]:fpr32 = SCVTFv1i32 [[COPY]]
+ ; CHECK: $s0 = COPY [[SCVTFv1i32_]]
%0(s32) = COPY $s0
%1(s32) = G_SITOFP %0
$s0 = COPY %1(s32)
@@ -276,8 +276,8 @@ body: |
; CHECK-LABEL: name: uitofp_s32_s32_fpr_fpr
; CHECK: [[COPY:%[0-9]+]]:fpr32 = COPY $s0
- ; CHECK: [[UCVTFv1i32:%[0-9]+]]:fpr32 = UCVTFv1i32 [[COPY]]
- ; CHECK: $s0 = COPY [[UCVTFv1i32]]
+ ; CHECK: [[UCVTFv1i32_:%[0-9]+]]:fpr32 = UCVTFv1i32 [[COPY]]
+ ; CHECK: $s0 = COPY [[UCVTFv1i32_]]
%0(s32) = COPY $s0
%1(s32) = G_UITOFP %0
$s0 = COPY %1(s32)
@@ -340,10 +340,10 @@ body: |
bb.0:
liveins: $s0
- ; CHECK-LABEL: name: sitofp_s64_s32_fpr
+ ; CHECK-LABEL: name: sitofp_s64_s32_fpr_both
; CHECK: [[COPY:%[0-9]+]]:fpr32 = COPY $s0
- ; CHECK: [[COPY2:%[0-9]+]]:gpr32 = COPY [[COPY]]
- ; CHECK: [[SCVTFUWDri:%[0-9]+]]:fpr64 = SCVTFUWDri [[COPY2]]
+ ; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY [[COPY]]
+ ; CHECK: [[SCVTFUWDri:%[0-9]+]]:fpr64 = SCVTFUWDri [[COPY1]]
; CHECK: $d0 = COPY [[SCVTFUWDri]]
%0(s32) = COPY $s0
%1(s64) = G_SITOFP %0
@@ -635,3 +635,155 @@ body: |
%1(s64) = G_FPTOUI %0
$x0 = COPY %1(s64)
...
+
+---
+name: sitofp_v2s64_v2s32
+legalized: true
+regBankSelected: true
+
+body: |
+ bb.0:
+ liveins: $d0
+
+ ; CHECK-LABEL: name: sitofp_v2s64_v2s32
+ ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
+ ; CHECK: [[SSHLLv2i32_shift:%[0-9]+]]:fpr128 = SSHLLv2i32_shift [[COPY]], 0
+ ; CHECK: [[SCVTFv2f64_:%[0-9]+]]:fpr128 = SCVTFv2f64 [[SSHLLv2i32_shift]]
+ ; CHECK: $q0 = COPY [[SCVTFv2f64_]]
+ %0:fpr(<2 x s32>) = COPY $d0
+ %1:fpr(<2 x s64>) = G_SITOFP %0
+ $q0 = COPY %1(<2 x s64>)
+...
+
+---
+name: uitofp_v2s64_v2s32
+legalized: true
+regBankSelected: true
+
+body: |
+ bb.0:
+ liveins: $d0
+
+ ; CHECK-LABEL: name: uitofp_v2s64_v2s32
+ ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
+ ; CHECK: [[USHLLv2i32_shift:%[0-9]+]]:fpr128 = USHLLv2i32_shift [[COPY]], 0
+ ; CHECK: [[UCVTFv2f64_:%[0-9]+]]:fpr128 = UCVTFv2f64 [[USHLLv2i32_shift]]
+ ; CHECK: $q0 = COPY [[UCVTFv2f64_]]
+ %0:fpr(<2 x s32>) = COPY $d0
+ %1:fpr(<2 x s64>) = G_UITOFP %0
+ $q0 = COPY %1(<2 x s64>)
+...
+
+---
+name: sitofp_v2s32_v2s64
+legalized: true
+regBankSelected: true
+
+body: |
+ bb.0:
+ liveins: $q0
+
+ ; CHECK-LABEL: name: sitofp_v2s32_v2s64
+ ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
+ ; CHECK: [[SCVTFv2f64_:%[0-9]+]]:fpr128 = SCVTFv2f64 [[COPY]]
+ ; CHECK: [[FCVTNv2i32_:%[0-9]+]]:fpr64 = FCVTNv2i32 [[SCVTFv2f64_]]
+ ; CHECK: $d0 = COPY [[FCVTNv2i32_]]
+ %0:fpr(<2 x s64>) = COPY $q0
+ %1:fpr(<2 x s32>) = G_SITOFP %0
+ $d0 = COPY %1(<2 x s32>)
+...
+
+---
+name: uitofp_v2s32_v2s64
+legalized: true
+regBankSelected: true
+
+body: |
+ bb.0:
+ liveins: $q0
+
+ ; CHECK-LABEL: name: uitofp_v2s32_v2s64
+ ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
+ ; CHECK: [[UCVTFv2f64_:%[0-9]+]]:fpr128 = UCVTFv2f64 [[COPY]]
+ ; CHECK: [[FCVTNv2i32_:%[0-9]+]]:fpr64 = FCVTNv2i32 [[UCVTFv2f64_]]
+ ; CHECK: $d0 = COPY [[FCVTNv2i32_]]
+ %0:fpr(<2 x s64>) = COPY $q0
+ %1:fpr(<2 x s32>) = G_UITOFP %0
+ $d0 = COPY %1(<2 x s32>)
+...
+
+---
+name: fptosi_v2s64_v2s32
+legalized: true
+regBankSelected: true
+
+body: |
+ bb.0:
+ liveins: $d0
+
+ ; CHECK-LABEL: name: fptosi_v2s64_v2s32
+ ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
+ ; CHECK: [[FCVTLv2i32_:%[0-9]+]]:fpr128 = FCVTLv2i32 [[COPY]]
+ ; CHECK: [[FCVTZSv2f64_:%[0-9]+]]:fpr128 = FCVTZSv2f64 [[FCVTLv2i32_]]
+ ; CHECK: $q0 = COPY [[FCVTZSv2f64_]]
+ %0:fpr(<2 x s32>) = COPY $d0
+ %1:fpr(<2 x s64>) = G_FPTOSI %0
+ $q0 = COPY %1(<2 x s64>)
+...
+
+---
+name: fptoui_v2s64_v2s32
+legalized: true
+regBankSelected: true
+
+body: |
+ bb.0:
+ liveins: $d0
+
+ ; CHECK-LABEL: name: fptoui_v2s64_v2s32
+ ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
+ ; CHECK: [[FCVTLv2i32_:%[0-9]+]]:fpr128 = FCVTLv2i32 [[COPY]]
+ ; CHECK: [[FCVTZUv2f64_:%[0-9]+]]:fpr128 = FCVTZUv2f64 [[FCVTLv2i32_]]
+ ; CHECK: $q0 = COPY [[FCVTZUv2f64_]]
+ %0:fpr(<2 x s32>) = COPY $d0
+ %1:fpr(<2 x s64>) = G_FPTOUI %0
+ $q0 = COPY %1(<2 x s64>)
+...
+
+---
+name: fptosi_v2s32_v2s64
+legalized: true
+regBankSelected: true
+
+body: |
+ bb.0:
+ liveins: $q0
+
+ ; CHECK-LABEL: name: fptosi_v2s32_v2s64
+ ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
+ ; CHECK: [[FCVTZSv2f64_:%[0-9]+]]:fpr128 = FCVTZSv2f64 [[COPY]]
+ ; CHECK: [[XTNv2i32_:%[0-9]+]]:fpr64 = XTNv2i32 [[FCVTZSv2f64_]]
+ ; CHECK: $d0 = COPY [[XTNv2i32_]]
+ %0:fpr(<2 x s64>) = COPY $q0
+ %1:fpr(<2 x s32>) = G_FPTOSI %0
+ $d0 = COPY %1(<2 x s32>)
+...
+
+---
+name: fptoui_v2s32_v2s64
+legalized: true
+regBankSelected: true
+
+body: |
+ bb.0:
+ liveins: $q0
+
+ ; CHECK-LABEL: name: fptoui_v2s32_v2s64
+ ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
+ ; CHECK: [[FCVTZUv2f64_:%[0-9]+]]:fpr128 = FCVTZUv2f64 [[COPY]]
+ ; CHECK: [[XTNv2i32_:%[0-9]+]]:fpr64 = XTNv2i32 [[FCVTZUv2f64_]]
+ ; CHECK: $d0 = COPY [[XTNv2i32_]]
+ %0:fpr(<2 x s64>) = COPY $q0
+ %1:fpr(<2 x s32>) = G_FPTOUI %0
+ $d0 = COPY %1(<2 x s32>)
+...
diff --git a/llvm/utils/TableGen/GlobalISelEmitter.cpp b/llvm/utils/TableGen/GlobalISelEmitter.cpp
index 8b0d8a663892d..23da0b83cc9f2 100644
--- a/llvm/utils/TableGen/GlobalISelEmitter.cpp
+++ b/llvm/utils/TableGen/GlobalISelEmitter.cpp
@@ -4464,7 +4464,6 @@ Expected<action_iterator> GlobalISelEmitter::importExplicitUseRenderer(
return failedImport(
"Dst pattern child def is an unsupported tablegen class");
}
-
return failedImport("Dst pattern child is an unsupported kind");
}
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