[llvm] ac1647c - AArch64: expand G_DIVREM operations in GlobalISel
Tim Northover via llvm-commits
llvm-commits at lists.llvm.org
Thu Apr 22 07:03:24 PDT 2021
Author: Tim Northover
Date: 2021-04-22T15:03:17+01:00
New Revision: ac1647cc805867df95b0c4d271ad20a353ba602c
URL: https://github.com/llvm/llvm-project/commit/ac1647cc805867df95b0c4d271ad20a353ba602c
DIFF: https://github.com/llvm/llvm-project/commit/ac1647cc805867df95b0c4d271ad20a353ba602c.diff
LOG: AArch64: expand G_DIVREM operations in GlobalISel
We don't have a specific instruction for these, so they should be expanded to
whatever separate division & multiplication is needed.
Added:
llvm/test/CodeGen/AArch64/GlobalISel/legalize-divrem.mir
Modified:
llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
llvm/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir
Removed:
################################################################################
diff --git a/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp b/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
index 18fe7d09a2f5f..70a9fbe52d9a9 100644
--- a/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
+++ b/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
@@ -159,7 +159,7 @@ AArch64LegalizerInfo::AArch64LegalizerInfo(const AArch64Subtarget &ST)
.widenScalarToNextPow2(0)
.scalarize(0);
- getActionDefinitionsBuilder({G_SREM, G_UREM})
+ getActionDefinitionsBuilder({G_SREM, G_UREM, G_SDIVREM, G_UDIVREM})
.lowerFor({s1, s8, s16, s32, s64});
getActionDefinitionsBuilder({G_SMULO, G_UMULO}).lowerFor({{s64, s1}});
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-divrem.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-divrem.mir
new file mode 100644
index 0000000000000..91a9d2234c88a
--- /dev/null
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-divrem.mir
@@ -0,0 +1,76 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple=aarch64-- -verify-machineinstrs -run-pass=legalizer %s -o - | FileCheck %s
+---
+name: test_udivrem_64
+body: |
+ bb.0.entry:
+ ; CHECK-LABEL: name: test_udivrem_64
+ ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
+ ; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY $x1
+ ; CHECK: [[UDIV:%[0-9]+]]:_(s64) = G_UDIV [[COPY]], [[COPY1]]
+ ; CHECK: [[MUL:%[0-9]+]]:_(s64) = G_MUL [[UDIV]], [[COPY1]]
+ ; CHECK: [[SUB:%[0-9]+]]:_(s64) = G_SUB [[COPY]], [[MUL]]
+ ; CHECK: $x0 = COPY [[UDIV]](s64)
+ ; CHECK: $x1 = COPY [[SUB]](s64)
+ %0:_(s64) = COPY $x0
+ %1:_(s64) = COPY $x1
+ %2:_(s64), %3:_(s64) = G_UDIVREM %0, %1
+ $x0 = COPY %2(s64)
+ $x1 = COPY %3(s64)
+
+...
+---
+name: test_sdivrem_32
+body: |
+ bb.0.entry:
+ ; CHECK-LABEL: name: test_sdivrem_32
+ ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
+ ; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY $x1
+ ; CHECK: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
+ ; CHECK: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64)
+ ; CHECK: [[SDIV:%[0-9]+]]:_(s32) = G_SDIV [[TRUNC]], [[TRUNC1]]
+ ; CHECK: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[SDIV]], [[TRUNC1]]
+ ; CHECK: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[TRUNC]], [[MUL]]
+ ; CHECK: $w0 = COPY [[SDIV]](s32)
+ ; CHECK: $w1 = COPY [[SUB]](s32)
+ %0:_(s64) = COPY $x0
+ %1:_(s64) = COPY $x1
+ %2:_(s32) = G_TRUNC %0(s64)
+ %3:_(s32) = G_TRUNC %1(s64)
+ %4:_(s32), %5:_(s32) = G_SDIVREM %2, %3
+ $w0 = COPY %4(s32)
+ $w1 = COPY %5(s32)
+
+...
+---
+name: test_sdivrem_8
+body: |
+ bb.0.entry:
+ ; CHECK-LABEL: name: test_sdivrem_8
+ ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
+ ; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY $x1
+ ; CHECK: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
+ ; CHECK: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[TRUNC]], 8
+ ; CHECK: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64)
+ ; CHECK: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[TRUNC1]], 8
+ ; CHECK: [[SDIV:%[0-9]+]]:_(s32) = G_SDIV [[SEXT_INREG]], [[SEXT_INREG1]]
+ ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[SDIV]](s32)
+ ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[TRUNC1]](s32)
+ ; CHECK: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[COPY2]], [[COPY3]]
+ ; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[TRUNC]](s32)
+ ; CHECK: [[COPY5:%[0-9]+]]:_(s32) = COPY [[MUL]](s32)
+ ; CHECK: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[COPY4]], [[COPY5]]
+ ; CHECK: [[COPY6:%[0-9]+]]:_(s32) = COPY [[SUB]](s32)
+ ; CHECK: $w0 = COPY [[COPY2]](s32)
+ ; CHECK: $w1 = COPY [[COPY6]](s32)
+ %0:_(s64) = COPY $x0
+ %1:_(s64) = COPY $x1
+ %2:_(s8) = G_TRUNC %0(s64)
+ %3:_(s8) = G_TRUNC %1(s64)
+ %4:_(s8), %5:_(s8) = G_SDIVREM %2, %3
+ %6:_(s32) = G_ANYEXT %4(s8)
+ %7:_(s32) = G_ANYEXT %5(s8)
+ $w0 = COPY %6(s32)
+ $w1 = COPY %7(s32)
+
+...
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir
index 79c46464cde6b..aa6e81693eeae 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir
@@ -46,12 +46,14 @@
# DEBUG-NEXT: .. the first uncovered imm index: 0, OK
#
# DEBUG-NEXT: G_SDIVREM (opcode {{[0-9]+}}): 1 type index, 0 imm indices
-# DEBUG-NEXT: .. type index coverage check SKIPPED: no rules defined
-# DEBUG-NEXT: .. imm index coverage check SKIPPED: no rules defined
+# DEBUG-NEXT: .. opcode {{[0-9]+}} is aliased to {{[0-9]+}}
+# DEBUG-NEXT: .. the first uncovered type index: 1, OK
+# DEBUG-NEXT: .. the first uncovered imm index: 0, OK
#
# DEBUG-NEXT: G_UDIVREM (opcode {{[0-9]+}}): 1 type index, 0 imm indices
-# DEBUG-NEXT: .. type index coverage check SKIPPED: no rules defined
-# DEBUG-NEXT: .. imm index coverage check SKIPPED: no rules defined
+# DEBUG-NEXT: .. opcode {{[0-9]+}} is aliased to {{[0-9]+}}
+# DEBUG-NEXT: .. the first uncovered type index: 1, OK
+# DEBUG-NEXT: .. the first uncovered imm index: 0, OK
#
# DEBUG-NEXT: G_AND (opcode {{[0-9]+}}): 1 type index, 0 imm indices
# DEBUG-NEXT: .. opcode {{[0-9]+}} is aliased to {{[0-9]+}}
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