[PATCH] D101015: [RISCV] Add assembler check to make temp register is different than dest register for vmsgeu.vx pseudo.

[Craig Topper via Phabricator via llvm-commits]

craig.topper updated this revision to Diff 339455.
craig.topper added a comment.
Herald added a subscriber: hiraditya.

Add the code change not just the test.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D101015/new/

https://reviews.llvm.org/D101015

Files:
  llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
  llvm/test/MC/RISCV/rvv/invalid.s


Index: llvm/test/MC/RISCV/rvv/invalid.s
===================================================================
--- llvm/test/MC/RISCV/rvv/invalid.s
+++ llvm/test/MC/RISCV/rvv/invalid.s
@@ -666,3 +666,9 @@
 
 vmsgeu.vx v2, v4, a0, v0.t, v0
 # CHECK-ERROR: invalid operand for instruction
+
+vmsge.vx v2, v4, a0, v0.t, v2
+# CHECK-ERROR: The temporary vector register cannot be the same as the destination register.
+
+vmsgeu.vx v2, v4, a0, v0.t, v2
+# CHECK-ERROR: The temporary vector register cannot be the same as the destination register.
Index: llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
===================================================================
--- llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
+++ llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
@@ -2461,6 +2461,17 @@
 
 bool RISCVAsmParser::validateInstruction(MCInst &Inst,
                                          OperandVector &Operands) {
+  if (Inst.getOpcode() == RISCV::PseudoVMSGEU_VX_M_T ||
+      Inst.getOpcode() == RISCV::PseudoVMSGE_VX_M_T) {
+    unsigned DestReg = Inst.getOperand(0).getReg();
+    unsigned TempReg = Inst.getOperand(1).getReg();
+    if (DestReg == TempReg) {
+      SMLoc Loc = Operands.back()->getStartLoc();
+      return Error(Loc, "The temporary vector register cannot be the same as "
+                        "the destination register.");
+    }
+  }
+
   const MCInstrDesc &MCID = MII.get(Inst.getOpcode());
   unsigned Constraints =
       (MCID.TSFlags & RISCVII::ConstraintMask) >> RISCVII::ConstraintShift;


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