[PATCH] D101015: [RISCV] Add assembler check to make temp register is different than dest register for vmsgeu.vx pseudo.

[Craig Topper via Phabricator via llvm-commits]

craig.topper created this revision.
craig.topper added reviewers: frasercrmck, evandro, HsiangKai, arcbbb, khchen, kito-cheng.
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craig.topper requested review of this revision.
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Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D101015

Files:
  llvm/test/MC/RISCV/rvv/invalid.s


Index: llvm/test/MC/RISCV/rvv/invalid.s
===================================================================
--- llvm/test/MC/RISCV/rvv/invalid.s
+++ llvm/test/MC/RISCV/rvv/invalid.s
@@ -666,3 +666,9 @@
 
 vmsgeu.vx v2, v4, a0, v0.t, v0
 # CHECK-ERROR: invalid operand for instruction
+
+vmsge.vx v2, v4, a0, v0.t, v2
+# CHECK-ERROR: The temporary vector register cannot be the same as the destination register.
+
+vmsgeu.vx v2, v4, a0, v0.t, v2
+# CHECK-ERROR: The temporary vector register cannot be the same as the destination register.


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