[PATCH] D100960: [AMDGPU] Fix typo in implicit operand lists

[Sebastian Neubauer via Phabricator via llvm-commits]

sebastian-ne added a comment.

Wow, how did you find that? The test changes look good to me.



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Comment at: llvm/test/CodeGen/AMDGPU/pei-scavenge-sgpr-carry-out.mir:35
+    ; CHECK: $exec = S_MOV_B64 killed $sgpr4_sgpr5
+    ; CHECK: $vgpr2 = V_WRITELANE_B32 $sgpr33, 0, undef $vgpr2
     ; CHECK: $sgpr33 = frame-setup S_ADD_U32 $sgpr32, 524224, implicit-def $scc
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arsenm wrote:
> Why is this use undef, and why is it saving the VGPR just saved to memory?
v2 is used as an SGPR spill register, so all lanes of v2 are first saved to memory (killing v2, as we do not care about it anymore), then s33 is saved into the first lane of v2.


Repository:
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  https://reviews.llvm.org/D100960/new/

https://reviews.llvm.org/D100960