[PATCH] D100925: [RISCV] Add IR intrinsics for vmsge(u). Support vector operands for all comparison intrinsics.

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


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Comment at: llvm/test/CodeGen/RISCV/rvv/vmsge-rv32.ll:976
+; CHECK-NEXT:    vsetvli a0, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vmxor.mm v0, v25, v9
+; CHECK-NEXT:    jalr zero, 0(ra)
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Note we end up using v9 as third operand of the vmxor instead of v0. But it's ok because we copied v9 to v0 before the vmslt.vx so v9 and v0 are the same value. Neither v9 or v0 were affected by the vmslt.vx.


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Comment at: llvm/test/CodeGen/RISCV/rvv/vmsge-rv32.ll:2491
+
+; Test cases where the mask and maskedoff are the same value.
+define <vscale x 1 x i1> @intrinsic_vmsge_maskedoff_mask_vx_nxv1i8_i8(<vscale x 1 x i1> %0, <vscale x 1 x i8> %1, i8 %2, i32 %3) nounwind {
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These are the test cases for when mask and maskedoff are the same value.


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D100925/new/

https://reviews.llvm.org/D100925