[PATCH] D100925: [RISCV] Add IR intrinsics for vmsge(u). Support vector operands for all comparison intrinsics.

[Craig Topper via Phabricator via llvm-commits]

craig.topper created this revision.
craig.topper added reviewers: HsiangKai, arcbbb, evandro, frasercrmck, rogfer01, khchen, kito-cheng.
Herald added subscribers: StephenFan, vkmr, luismarques, apazos, sameer.abuasal, s.egerton, Jim, benna, psnobl, jocewei, PkmX, the_o, brucehoult, MartinMosbeck, edward-jones, zzheng, jrtc27, shiva0217, niosHD, sabuasal, JDevlieghere, simoncook, johnrusso, rbar, asb, hiraditya.
craig.topper requested review of this revision.
Herald added a subscriber: MaskRay.
Herald added a project: LLVM.

Previously we mostly support .vv operands for intrinsics where
there was a .vv instruction. Othewise we only supported scalar
operands for the .vx and .vf instructions. The C interface defines
.vv intrinsics even when an instruction doesn't exist since the
operands can be swapped to use another instruction. We were going
to handle this in the frontend, but I think it makes the IR interface
confusing. So this patch proposes to handle all the .vv cases in
the backend by swapping operands where needed.

I've also added vmsge(u) intrinsics with support .vv, .vx, and .vi.
.vv will swap operands and use vmsle().vv. .vi will adjust the
immediate and use .vmsgt(u).vi. For .vx we need to use the
two multiple instruction sequences from the V extension spec.

For unmasked vmsge(u).vx we use
 vmslt{u}.vx vd, va, x

For cases where mask and maskedoff are the same value then we have
vmsge{u}.vx v0, va, x, v0.t which is the vd==v0 case whichi
requires a temporary so we use:
 vmslt{u}.vx vt, va, x;  vmandnot.mm vd, vd, vt

For other masked cases we use this sequence.

  vmslt{u}.vx vd, va, x, v0.t; vmxor.mm vd, vd, v0

We trust that register allocation will prevent vd in vmslt{u}.vx
from being v0 since v0 is still needed by the vmxor.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D100925

Files:
  llvm/include/llvm/IR/IntrinsicsRISCV.td
  llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
  llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
  llvm/test/CodeGen/RISCV/rvv/vmfge-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vmfge-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vmfgt-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vmfgt-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vmsge-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vmsge-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vmsgeu-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vmsgeu-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vmsgt-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vmsgt-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vmsgtu-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vmsgtu-rv64.ll