[llvm] 21a8b9d - [ARM] Limit PerformExtractEltToVMOVRRD to when f64 is legal.

[David Green via llvm-commits]

Author: David Green
Date: 2021-04-20T16:24:36+01:00
New Revision: 21a8b9d9e9e110fe82728226f185a35e15d1af0d

URL: https://github.com/llvm/llvm-project/commit/21a8b9d9e9e110fe82728226f185a35e15d1af0d
DIFF: https://github.com/llvm/llvm-project/commit/21a8b9d9e9e110fe82728226f185a35e15d1af0d.diff

LOG: [ARM] Limit PerformExtractEltToVMOVRRD to when f64 is legal.

The generic SoftFloatVectorExtract.ll test was failing when run on arm
machines, as it tries to create a f64 under soft float. Limit the
transform to when f64 is legal.

Also add a missing override, as reported in D100244.

Added: 
    llvm/test/CodeGen/ARM/SoftFloatVectorExtract.ll

Modified: 
    llvm/lib/Target/ARM/ARMBaseRegisterInfo.h
    llvm/lib/Target/ARM/ARMISelLowering.cpp

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/ARM/ARMBaseRegisterInfo.h b/llvm/lib/Target/ARM/ARMBaseRegisterInfo.h
index d29535bb91e5..57d7842c63ca 100644
--- a/llvm/lib/Target/ARM/ARMBaseRegisterInfo.h
+++ b/llvm/lib/Target/ARM/ARMBaseRegisterInfo.h
@@ -213,7 +213,7 @@ class ARMBaseRegisterInfo : public ARMGenRegisterInfo {
   bool shouldRewriteCopySrc(const TargetRegisterClass *DefRC,
                             unsigned DefSubReg,
                             const TargetRegisterClass *SrcRC,
-                            unsigned SrcSubReg) const;
+                            unsigned SrcSubReg) const override;
 };
 
 } // end namespace llvm

diff  --git a/llvm/lib/Target/ARM/ARMISelLowering.cpp b/llvm/lib/Target/ARM/ARMISelLowering.cpp
index 5084860a728a..e5f47939055e 100644
--- a/llvm/lib/Target/ARM/ARMISelLowering.cpp
+++ b/llvm/lib/Target/ARM/ARMISelLowering.cpp
@@ -14090,7 +14090,8 @@ PerformExtractEltToVMOVRRD(SDNode *N, TargetLowering::DAGCombinerInfo &DCI) {
   EVT VT = N->getValueType(0);
   SDLoc dl(N);
 
-  if (!DCI.isAfterLegalizeDAG() || VT != MVT::i32)
+  if (!DCI.isAfterLegalizeDAG() || VT != MVT::i32 ||
+      !DCI.DAG.getTargetLoweringInfo().isTypeLegal(MVT::f64))
     return SDValue();
 
   SDValue Ext = SDValue(N, 0);

diff  --git a/llvm/test/CodeGen/ARM/SoftFloatVectorExtract.ll b/llvm/test/CodeGen/ARM/SoftFloatVectorExtract.ll
new file mode 100644
index 000000000000..b27c0ddbb4e9
--- /dev/null
+++ b/llvm/test/CodeGen/ARM/SoftFloatVectorExtract.ll
@@ -0,0 +1,23 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=armv7a-linux-gnu < %s | FileCheck %s
+
+; Copied from llvm/test/CodeGen/Generic/2009-03-29-SoftFloatVectorExtract.ll,
+; making sure that soft float extract works on v7a soft float triples.
+
+ at m = external global <2 x double>
+
+define double @vector_ex() nounwind #0 {
+; CHECK-LABEL: vector_ex:
+; CHECK:       @ %bb.0:
+; CHECK-NEXT:    movw r0, :lower16:m
+; CHECK-NEXT:    movt r0, :upper16:m
+; CHECK-NEXT:    vld1.64 {d16, d17}, [r0]
+; CHECK-NEXT:    vmov.32 r0, d17[0]
+; CHECK-NEXT:    vmov.32 r1, d17[1]
+; CHECK-NEXT:    bx lr
+       %v = load <2 x double>, <2 x double>* @m
+       %x = extractelement <2 x double> %v, i32 1
+       ret double %x
+}
+
+attributes #0 = { "use-soft-float" = "true" }