[PATCH] D100767: [RISCV][test] Add a new test of addition

[Ben Shi via Phabricator via llvm-commits]

benshi001 created this revision.
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Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D100767

Files:
  llvm/test/CodeGen/RISCV/add-imm.ll


Index: llvm/test/CodeGen/RISCV/add-imm.ll
===================================================================
--- llvm/test/CodeGen/RISCV/add-imm.ll
+++ llvm/test/CodeGen/RISCV/add-imm.ll
@@ -150,6 +150,23 @@
   ret i32 %1
 }
 
+define signext i32 @add32_sext_accept(i32 signext %a) nounwind {
+; RV32I-LABEL: add32_sext_accept:
+; RV32I:       # %bb.0:
+; RV32I-NEXT:    addi a0, a0, 1500
+; RV32I-NEXT:    addi a0, a0, 1499
+; RV32I-NEXT:    ret
+;
+; RV64I-LABEL: add32_sext_accept:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    lui a1, 1
+; RV64I-NEXT:    addiw a1, a1, -1097
+; RV64I-NEXT:    addw a0, a0, a1
+; RV64I-NEXT:    ret
+  %1 = add i32 %a, 2999
+  ret i32 %1
+}
+
 define i64 @add64_accept(i64 %a) nounwind {
 ; RV32I-LABEL: add64_accept:
 ; RV32I:       # %bb.0:


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