[PATCH] D100244: [ARM] Create VMOVRRD from adjacent vector extracts

[Dave Green via Phabricator via llvm-commits]

dmgreen marked an inline comment as done.
dmgreen added inline comments.


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Comment at: llvm/lib/Target/ARM/ARMISelLowering.cpp:14207
+           isa<ConstantSDNode>(V->getOperand(1)) &&
+           V->getConstantOperandVal(1) == Lane + 1;
+  });
----------------
SjoerdMeijer wrote:
> SjoerdMeijer wrote:
> > Out of curiousity, this means we recognise:
> > 
> >   vmov.32 r3, d18[0]
> >   vmov.32 r2, d18[1]
> > 
> > but not:
> > 
> >   vmov.32 r2, d18[1]
> >   vmov.32 r3, d18[0]
> > 
> > ?
> Just out of u
It will create `vmov r2, r3, d18`, so should handle either. We are dealing with a DAG, so can start from the even lane and find the odd one. They don't have a fixed order (And we don't have fixed registers yet.)


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  https://reviews.llvm.org/D100244/new/

https://reviews.llvm.org/D100244