[PATCH] D100527: [AArch64][SVE] More unpredicated ld1/st1 patterns for reg+reg addressing modes

[Paul Walker via Phabricator via llvm-commits]

paulwalker-arm added a comment.

Sounds sensible to me but wonder if there's a nicer way to create the patterns as it seems we're likely to have a significant number of patterns targeting the same instructions. Do you think it's possible to have something like load_8 match all things where LD1_B (reg+reg) can be used?


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D100527/new/

https://reviews.llvm.org/D100527