[PATCH] D100280: [RISCV] Implement COPY for Zvlsseg registers

[ShihPo Hung via Phabricator via llvm-commits]

arcbbb updated this revision to Diff 337011.
arcbbb added a comment.

Address Craig's comment.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D100280/new/

https://reviews.llvm.org/D100280

Files:
  llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
  llvm/test/CodeGen/RISCV/rvv/zvlsseg-copy.mir

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