[PATCH] D100280: [RISCV] Implement COPY for Zvlsseg registers

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


================
Comment at: llvm/lib/Target/RISCV/RISCVInstrInfo.cpp:146
+    IsScalableVector = false;
+  } else if (RISCV::VRRegClass.contains(DstReg, SrcReg))
     Opc = RISCV::PseudoVMV1R_V;
----------------
Consistently use curly braces on all the blocks.


================
Comment at: llvm/lib/Target/RISCV/RISCVInstrInfo.cpp:214
+  if (IsScalableVector) {
+    if (NF == 1)
+      BuildMI(MBB, MBBI, DL, get(Opc), DstReg)
----------------
Put curly braces on this to match the else.


================
Comment at: llvm/lib/Target/RISCV/RISCVInstrInfo.cpp:235
+    }
+  } else
     BuildMI(MBB, MBBI, DL, get(Opc), DstReg)
----------------
Curly braces around this else to match the if


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D100280/new/

https://reviews.llvm.org/D100280