[PATCH] D100300: [AMDGPU] Refactor ds_read/ds_write related select code for better readability.

[Stanislav Mekhanoshin via Phabricator via llvm-commits]

rampitec added inline comments.


================
Comment at: llvm/lib/Target/AMDGPU/SIISelLowering.cpp:1431
     if (Size == 96) {
-      // ds_read/write_b96 require 16-byte alignment on gfx8 and older.
-      bool Aligned = Alignment >= Align(16);
+      // 12 byte accessing via ds_read/write_b96 require 16-byte alignment.
+      bool AlignedBy16 = Alignment >= Align(16);
----------------
It drops the comment about gfx8 and older which is probably still relevant.


================
Comment at: llvm/lib/Target/AMDGPU/SIISelLowering.cpp:1439
     if (Size == 128) {
-      // ds_read/write_b128 require 16-byte alignment on gfx8 and older, but we
-      // can do a 8 byte aligned, 16 byte access in a single operation using
+      // 16 byte accessing via ds_read/write_b128 require 16-byte alignment, but
+      // we can do a 8 byte aligned, 16 byte access in a single operation using
----------------
Same here.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D100300/new/

https://reviews.llvm.org/D100300