[PATCH] D100096: [RISCV] Support vector SET[U]LT and SET[U]GE with splatted immediates

[Fraser Cormack via Phabricator via llvm-commits]

frasercrmck marked an inline comment as done.
frasercrmck added inline comments.


================
Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td:433
+defm "" : VPatIntegerSetCCSDNode_VIPlus1<SETLT, "PseudoVMSLE">;
+defm "" : VPatIntegerSetCCSDNode_VIPlus1<SETULT, "PseudoVMSLEU">;
 
----------------
craig.topper wrote:
> Are we confident that we'll never see SETULT/SETUGE with a 0 splat? It doesn't happen for simple cases, but I wonder if the constant can appear later and our target specific nodes like RISCVISD::VMV_V_X_VL or RISCVISD::SPLAT_VECTOR_I64 can prevent setcc optimizations from seeing it.
Yes, you're right. I've fixed that now, and added a couple of tests using the `vmv.v.x` intrinsic to check it's not misoptimized.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D100096/new/

https://reviews.llvm.org/D100096