[llvm] bc0e052 - [RISCV] Teach targetShrinkDemandedConstant to preserve (and X, 0xffff) when zext.h is supported.

[Craig Topper via llvm-commits]

Author: Craig Topper
Date: 2021-04-11T10:03:35-07:00
New Revision: bc0e0527305d41bc55b27c60581749cb3ebdd5af

URL: https://github.com/llvm/llvm-project/commit/bc0e0527305d41bc55b27c60581749cb3ebdd5af
DIFF: https://github.com/llvm/llvm-project/commit/bc0e0527305d41bc55b27c60581749cb3ebdd5af.diff

LOG: [RISCV] Teach targetShrinkDemandedConstant to preserve (and X, 0xffff) when zext.h is supported.

Similar to what we do for zext.w.

Disable the (srl (and X, 0xffff), C) custom isel when zext.h is
available.

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
    llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    llvm/lib/Target/RISCV/RISCVInstrInfoB.td
    llvm/test/CodeGen/RISCV/rv32zbb-zbp.ll
    llvm/test/CodeGen/RISCV/rv64zbb-zbp.ll

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
index e20a7c3c6777..7b48e2c199a4 100644
--- a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
@@ -420,6 +420,9 @@ void RISCVDAGToDAGISel::Select(SDNode *Node) {
     return;
   }
   case ISD::SRL: {
+    // We don't need this transform if zext.h is supported.
+    if (Subtarget->hasStdExtZbb() || Subtarget->hasStdExtZbp())
+      break;
     // Optimize (srl (and X, 0xffff), C) -> (srli (slli X, 16), 16 + C).
     // Taking into account that the 0xffff may have had lower bits unset by
     // SimplifyDemandedBits. This avoids materializing the 0xffff immediate.

diff  --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index 209d1aae4eb8..b02140a7ada9 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -5238,6 +5238,13 @@ bool RISCVTargetLowering::targetShrinkDemandedConstant(
   if (ShrunkMask.isSignedIntN(12))
     return false;
 
+  // Preserve (and X, 0xffff) when zext.h is supported.
+  if (Subtarget.hasStdExtZbb() || Subtarget.hasStdExtZbp()) {
+    APInt NewMask = APInt(Mask.getBitWidth(), 0xffff);
+    if (IsLegalMask(NewMask))
+      return UseMask(NewMask);
+  }
+
   // Try to preserve (and X, 0xffffffff), the (zext_inreg X, i32) pattern.
   if (VT == MVT::i64) {
     APInt NewMask = APInt(64, 0xffffffff);

diff  --git a/llvm/lib/Target/RISCV/RISCVInstrInfoB.td b/llvm/lib/Target/RISCV/RISCVInstrInfoB.td
index 5d903432cd68..df2d2b6f8784 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoB.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoB.td
@@ -827,7 +827,7 @@ def : Pat<(i64 (or (and GPR:$rs2, 0xFFFFFFFF00000000), (srl GPR:$rs1, (i64 32)))
           (PACKU GPR:$rs1, GPR:$rs2)>;
 }
 let Predicates = [HasStdExtZbp] in
-def : Pat<(or (and (shl GPR:$rs2, (XLenVT 8)), 0xFF00),
+def : Pat<(or (and (shl GPR:$rs2, (XLenVT 8)), 0xFFFF),
               (and GPR:$rs1, 0x00FF)),
           (PACKH GPR:$rs1, GPR:$rs2)>;
 

diff  --git a/llvm/test/CodeGen/RISCV/rv32zbb-zbp.ll b/llvm/test/CodeGen/RISCV/rv32zbb-zbp.ll
index 3f827a0fbe7f..18cca70b11b5 100644
--- a/llvm/test/CodeGen/RISCV/rv32zbb-zbp.ll
+++ b/llvm/test/CodeGen/RISCV/rv32zbb-zbp.ll
@@ -810,20 +810,20 @@ define i16 @srli_i16(i16 %a) nounwind {
 ;
 ; RV32IB-LABEL: srli_i16:
 ; RV32IB:       # %bb.0:
-; RV32IB-NEXT:    slli a0, a0, 16
-; RV32IB-NEXT:    srli a0, a0, 22
+; RV32IB-NEXT:    zext.h a0, a0
+; RV32IB-NEXT:    srli a0, a0, 6
 ; RV32IB-NEXT:    ret
 ;
 ; RV32IBB-LABEL: srli_i16:
 ; RV32IBB:       # %bb.0:
-; RV32IBB-NEXT:    slli a0, a0, 16
-; RV32IBB-NEXT:    srli a0, a0, 22
+; RV32IBB-NEXT:    zext.h a0, a0
+; RV32IBB-NEXT:    srli a0, a0, 6
 ; RV32IBB-NEXT:    ret
 ;
 ; RV32IBP-LABEL: srli_i16:
 ; RV32IBP:       # %bb.0:
-; RV32IBP-NEXT:    slli a0, a0, 16
-; RV32IBP-NEXT:    srli a0, a0, 22
+; RV32IBP-NEXT:    zext.h a0, a0
+; RV32IBP-NEXT:    srli a0, a0, 6
 ; RV32IBP-NEXT:    ret
   %1 = lshr i16 %a, 6
   ret i16 %1

diff  --git a/llvm/test/CodeGen/RISCV/rv64zbb-zbp.ll b/llvm/test/CodeGen/RISCV/rv64zbb-zbp.ll
index efaf8fc92299..da2c5652a0ac 100644
--- a/llvm/test/CodeGen/RISCV/rv64zbb-zbp.ll
+++ b/llvm/test/CodeGen/RISCV/rv64zbb-zbp.ll
@@ -675,20 +675,20 @@ define i16 @srli_i16(i16 %a) nounwind {
 ;
 ; RV64IB-LABEL: srli_i16:
 ; RV64IB:       # %bb.0:
-; RV64IB-NEXT:    slliw a0, a0, 16
-; RV64IB-NEXT:    srliw a0, a0, 22
+; RV64IB-NEXT:    zext.h a0, a0
+; RV64IB-NEXT:    srli a0, a0, 6
 ; RV64IB-NEXT:    ret
 ;
 ; RV64IBB-LABEL: srli_i16:
 ; RV64IBB:       # %bb.0:
-; RV64IBB-NEXT:    slliw a0, a0, 16
-; RV64IBB-NEXT:    srliw a0, a0, 22
+; RV64IBB-NEXT:    zext.h a0, a0
+; RV64IBB-NEXT:    srli a0, a0, 6
 ; RV64IBB-NEXT:    ret
 ;
 ; RV64IBP-LABEL: srli_i16:
 ; RV64IBP:       # %bb.0:
-; RV64IBP-NEXT:    slliw a0, a0, 16
-; RV64IBP-NEXT:    srliw a0, a0, 22
+; RV64IBP-NEXT:    zext.h a0, a0
+; RV64IBP-NEXT:    srli a0, a0, 6
 ; RV64IBP-NEXT:    ret
   %1 = lshr i16 %a, 6
   ret i16 %1