[llvm] 48d69ed - [RISCV] Add i8 and i16 srli and srai tests to Zbb/Zbp test files. NFC
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Sun Apr 11 10:19:15 PDT 2021
Author: Craig Topper
Date: 2021-04-11T10:00:38-07:00
New Revision: 48d69edadef1e4155106b183cd7219a1086454fe
URL: https://github.com/llvm/llvm-project/commit/48d69edadef1e4155106b183cd7219a1086454fe
DIFF: https://github.com/llvm/llvm-project/commit/48d69edadef1e4155106b183cd7219a1086454fe.diff
LOG: [RISCV] Add i8 and i16 srli and srai tests to Zbb/Zbp test files. NFC
These require the input to be zero or sign extended. If we have
sext.b, sext.h or zext.h instructions we can use them. Otherwise
we need to use a pair of shifts to accomplish the zero/sign extend
and the final shift.
We don't currently use zext.h when it is available.
Added:
Modified:
llvm/test/CodeGen/RISCV/rv32zbb-zbp.ll
llvm/test/CodeGen/RISCV/rv64zbb-zbp.ll
Removed:
################################################################################
diff --git a/llvm/test/CodeGen/RISCV/rv32zbb-zbp.ll b/llvm/test/CodeGen/RISCV/rv32zbb-zbp.ll
index c2e4f708bbe9..3f827a0fbe7f 100644
--- a/llvm/test/CodeGen/RISCV/rv32zbb-zbp.ll
+++ b/llvm/test/CodeGen/RISCV/rv32zbb-zbp.ll
@@ -744,3 +744,115 @@ define i64 @rori_i64_fshr(i64 %a) nounwind {
%1 = tail call i64 @llvm.fshr.i64(i64 %a, i64 %a, i64 63)
ret i64 %1
}
+
+define i8 @srli_i8(i8 %a) nounwind {
+; RV32I-LABEL: srli_i8:
+; RV32I: # %bb.0:
+; RV32I-NEXT: andi a0, a0, 192
+; RV32I-NEXT: srli a0, a0, 6
+; RV32I-NEXT: ret
+;
+; RV32IB-LABEL: srli_i8:
+; RV32IB: # %bb.0:
+; RV32IB-NEXT: andi a0, a0, 192
+; RV32IB-NEXT: srli a0, a0, 6
+; RV32IB-NEXT: ret
+;
+; RV32IBB-LABEL: srli_i8:
+; RV32IBB: # %bb.0:
+; RV32IBB-NEXT: andi a0, a0, 192
+; RV32IBB-NEXT: srli a0, a0, 6
+; RV32IBB-NEXT: ret
+;
+; RV32IBP-LABEL: srli_i8:
+; RV32IBP: # %bb.0:
+; RV32IBP-NEXT: andi a0, a0, 192
+; RV32IBP-NEXT: srli a0, a0, 6
+; RV32IBP-NEXT: ret
+ %1 = lshr i8 %a, 6
+ ret i8 %1
+}
+
+define i8 @srai_i8(i8 %a) nounwind {
+; RV32I-LABEL: srai_i8:
+; RV32I: # %bb.0:
+; RV32I-NEXT: slli a0, a0, 24
+; RV32I-NEXT: srai a0, a0, 29
+; RV32I-NEXT: ret
+;
+; RV32IB-LABEL: srai_i8:
+; RV32IB: # %bb.0:
+; RV32IB-NEXT: sext.b a0, a0
+; RV32IB-NEXT: srai a0, a0, 5
+; RV32IB-NEXT: ret
+;
+; RV32IBB-LABEL: srai_i8:
+; RV32IBB: # %bb.0:
+; RV32IBB-NEXT: sext.b a0, a0
+; RV32IBB-NEXT: srai a0, a0, 5
+; RV32IBB-NEXT: ret
+;
+; RV32IBP-LABEL: srai_i8:
+; RV32IBP: # %bb.0:
+; RV32IBP-NEXT: slli a0, a0, 24
+; RV32IBP-NEXT: srai a0, a0, 29
+; RV32IBP-NEXT: ret
+ %1 = ashr i8 %a, 5
+ ret i8 %1
+}
+
+define i16 @srli_i16(i16 %a) nounwind {
+; RV32I-LABEL: srli_i16:
+; RV32I: # %bb.0:
+; RV32I-NEXT: slli a0, a0, 16
+; RV32I-NEXT: srli a0, a0, 22
+; RV32I-NEXT: ret
+;
+; RV32IB-LABEL: srli_i16:
+; RV32IB: # %bb.0:
+; RV32IB-NEXT: slli a0, a0, 16
+; RV32IB-NEXT: srli a0, a0, 22
+; RV32IB-NEXT: ret
+;
+; RV32IBB-LABEL: srli_i16:
+; RV32IBB: # %bb.0:
+; RV32IBB-NEXT: slli a0, a0, 16
+; RV32IBB-NEXT: srli a0, a0, 22
+; RV32IBB-NEXT: ret
+;
+; RV32IBP-LABEL: srli_i16:
+; RV32IBP: # %bb.0:
+; RV32IBP-NEXT: slli a0, a0, 16
+; RV32IBP-NEXT: srli a0, a0, 22
+; RV32IBP-NEXT: ret
+ %1 = lshr i16 %a, 6
+ ret i16 %1
+}
+
+define i16 @srai_i16(i16 %a) nounwind {
+; RV32I-LABEL: srai_i16:
+; RV32I: # %bb.0:
+; RV32I-NEXT: slli a0, a0, 16
+; RV32I-NEXT: srai a0, a0, 25
+; RV32I-NEXT: ret
+;
+; RV32IB-LABEL: srai_i16:
+; RV32IB: # %bb.0:
+; RV32IB-NEXT: sext.h a0, a0
+; RV32IB-NEXT: srai a0, a0, 9
+; RV32IB-NEXT: ret
+;
+; RV32IBB-LABEL: srai_i16:
+; RV32IBB: # %bb.0:
+; RV32IBB-NEXT: sext.h a0, a0
+; RV32IBB-NEXT: srai a0, a0, 9
+; RV32IBB-NEXT: ret
+;
+; RV32IBP-LABEL: srai_i16:
+; RV32IBP: # %bb.0:
+; RV32IBP-NEXT: slli a0, a0, 16
+; RV32IBP-NEXT: srai a0, a0, 25
+; RV32IBP-NEXT: ret
+ %1 = ashr i16 %a, 9
+ ret i16 %1
+}
diff --git a/llvm/test/CodeGen/RISCV/rv64zbb-zbp.ll b/llvm/test/CodeGen/RISCV/rv64zbb-zbp.ll
index b92abd58721e..efaf8fc92299 100644
--- a/llvm/test/CodeGen/RISCV/rv64zbb-zbp.ll
+++ b/llvm/test/CodeGen/RISCV/rv64zbb-zbp.ll
@@ -609,3 +609,115 @@ define i64 @rori_i64_fshr(i64 %a) nounwind {
%1 = tail call i64 @llvm.fshr.i64(i64 %a, i64 %a, i64 63)
ret i64 %1
}
+
+define i8 @srli_i8(i8 %a) nounwind {
+; RV64I-LABEL: srli_i8:
+; RV64I: # %bb.0:
+; RV64I-NEXT: andi a0, a0, 192
+; RV64I-NEXT: srli a0, a0, 6
+; RV64I-NEXT: ret
+;
+; RV64IB-LABEL: srli_i8:
+; RV64IB: # %bb.0:
+; RV64IB-NEXT: andi a0, a0, 192
+; RV64IB-NEXT: srli a0, a0, 6
+; RV64IB-NEXT: ret
+;
+; RV64IBB-LABEL: srli_i8:
+; RV64IBB: # %bb.0:
+; RV64IBB-NEXT: andi a0, a0, 192
+; RV64IBB-NEXT: srli a0, a0, 6
+; RV64IBB-NEXT: ret
+;
+; RV64IBP-LABEL: srli_i8:
+; RV64IBP: # %bb.0:
+; RV64IBP-NEXT: andi a0, a0, 192
+; RV64IBP-NEXT: srli a0, a0, 6
+; RV64IBP-NEXT: ret
+ %1 = lshr i8 %a, 6
+ ret i8 %1
+}
+
+define i8 @srai_i8(i8 %a) nounwind {
+; RV64I-LABEL: srai_i8:
+; RV64I: # %bb.0:
+; RV64I-NEXT: slli a0, a0, 56
+; RV64I-NEXT: srai a0, a0, 61
+; RV64I-NEXT: ret
+;
+; RV64IB-LABEL: srai_i8:
+; RV64IB: # %bb.0:
+; RV64IB-NEXT: sext.b a0, a0
+; RV64IB-NEXT: srai a0, a0, 5
+; RV64IB-NEXT: ret
+;
+; RV64IBB-LABEL: srai_i8:
+; RV64IBB: # %bb.0:
+; RV64IBB-NEXT: sext.b a0, a0
+; RV64IBB-NEXT: srai a0, a0, 5
+; RV64IBB-NEXT: ret
+;
+; RV64IBP-LABEL: srai_i8:
+; RV64IBP: # %bb.0:
+; RV64IBP-NEXT: slli a0, a0, 56
+; RV64IBP-NEXT: srai a0, a0, 61
+; RV64IBP-NEXT: ret
+ %1 = ashr i8 %a, 5
+ ret i8 %1
+}
+
+define i16 @srli_i16(i16 %a) nounwind {
+; RV64I-LABEL: srli_i16:
+; RV64I: # %bb.0:
+; RV64I-NEXT: slliw a0, a0, 16
+; RV64I-NEXT: srliw a0, a0, 22
+; RV64I-NEXT: ret
+;
+; RV64IB-LABEL: srli_i16:
+; RV64IB: # %bb.0:
+; RV64IB-NEXT: slliw a0, a0, 16
+; RV64IB-NEXT: srliw a0, a0, 22
+; RV64IB-NEXT: ret
+;
+; RV64IBB-LABEL: srli_i16:
+; RV64IBB: # %bb.0:
+; RV64IBB-NEXT: slliw a0, a0, 16
+; RV64IBB-NEXT: srliw a0, a0, 22
+; RV64IBB-NEXT: ret
+;
+; RV64IBP-LABEL: srli_i16:
+; RV64IBP: # %bb.0:
+; RV64IBP-NEXT: slliw a0, a0, 16
+; RV64IBP-NEXT: srliw a0, a0, 22
+; RV64IBP-NEXT: ret
+ %1 = lshr i16 %a, 6
+ ret i16 %1
+}
+
+define i16 @srai_i16(i16 %a) nounwind {
+; RV64I-LABEL: srai_i16:
+; RV64I: # %bb.0:
+; RV64I-NEXT: slli a0, a0, 48
+; RV64I-NEXT: srai a0, a0, 57
+; RV64I-NEXT: ret
+;
+; RV64IB-LABEL: srai_i16:
+; RV64IB: # %bb.0:
+; RV64IB-NEXT: sext.h a0, a0
+; RV64IB-NEXT: srai a0, a0, 9
+; RV64IB-NEXT: ret
+;
+; RV64IBB-LABEL: srai_i16:
+; RV64IBB: # %bb.0:
+; RV64IBB-NEXT: sext.h a0, a0
+; RV64IBB-NEXT: srai a0, a0, 9
+; RV64IBB-NEXT: ret
+;
+; RV64IBP-LABEL: srai_i16:
+; RV64IBP: # %bb.0:
+; RV64IBP-NEXT: slli a0, a0, 48
+; RV64IBP-NEXT: srai a0, a0, 57
+; RV64IBP-NEXT: ret
+ %1 = ashr i16 %a, 9
+ ret i16 %1
+}
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