[PATCH] D100115: [RISCV] Add missing part of instruction vmsge {u}. VX

[Craig Topper via Phabricator via llvm-commits]

craig.topper added a comment.

In D100115#2678649 <https://reviews.llvm.org/D100115#2678649>, @HsiangKai wrote:

> Do we need this case? Case 4 is any vd. It means (vd == v0) || (vd != v0), right? These two cases are already covered by case 2 and case 3.

I think this is the case that a temp register is provided and the destination isn't v0. The user probably should use case 2 by not providing the temp register. But if they give the temp register should we accept it and match the spec or error for the destination not being v0(what we currently do)?


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D100115/new/

https://reviews.llvm.org/D100115