[PATCH] D100115: [RISCV] Add missing part of instruction vmsge {u}. VX

[Hsiangkai Wang via Phabricator via llvm-commits]

HsiangKai added a comment.

Do we need this case? Case 4 is any vd. It means (vd == v0) || (vd != v0), right? These two cases are already covered by case 2 and case 3.


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  https://reviews.llvm.org/D100115/new/

https://reviews.llvm.org/D100115