[PATCH] D100096: [RISCV] Support vector SET[U]LT and SET[U]GE with splatted immediates

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


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Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td:433
+defm "" : VPatIntegerSetCCSDNode_VIPlus1<SETLT, "PseudoVMSLE">;
+defm "" : VPatIntegerSetCCSDNode_VIPlus1<SETULT, "PseudoVMSLEU">;
 
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Are we confident that we'll never see SETULT/SETUGE with a 0 splat? It doesn't happen for simple cases, but I wonder if the constant can appear later and our target specific nodes like RISCVISD::VMV_V_X_VL or RISCVISD::SPLAT_VECTOR_I64 can prevent setcc optimizations from seeing it.


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D100096/new/

https://reviews.llvm.org/D100096