[PATCH] D100030: [RISCV] Support OR/XOR/AND reductions on vector masks

Fraser Cormack via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Wed Apr 7 11:44:56 PDT 2021


frasercrmck marked 3 inline comments as done.
frasercrmck added inline comments.


================
Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:3041
+  case ISD::VECREDUCE_XOR: {
+    // vpopc != 0 && vpopc != vl
+    Vec = DAG.getNode(RISCVISD::VPOPC_VL, DL, XLenVT, Vec, Mask, VL);
----------------
craig.topper wrote:
> frasercrmck wrote:
> > craig.topper wrote:
> > > This doesn't make sense to me. I was thinking xor should be (vpopc & 1) != 0. Meaning it's 1 when there is an odd number of set bits.
> > Hmm yes I think I've somehow got some wires crossed. Would we assert that vector length is even or does that assumption run deep enough already?
> Doesn't (vpopc & 1) != 0 still work for odd VL as long as the vpopc was given the odd VL and only summed VL bits?
Oh dear, yes, I think I'd better just stop for the day! Should we generate `!= 0` in even though the `& 1` suffices? It's optimized out but it's arguably more readable.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D100030/new/

https://reviews.llvm.org/D100030



More information about the llvm-commits mailing list