[PATCH] D100030: [RISCV] Support OR/XOR/AND reductions on vector masks

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


================
Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:3041
+  case ISD::VECREDUCE_XOR: {
+    // vpopc != 0 && vpopc != vl
+    Vec = DAG.getNode(RISCVISD::VPOPC_VL, DL, XLenVT, Vec, Mask, VL);
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frasercrmck wrote:
> craig.topper wrote:
> > This doesn't make sense to me. I was thinking xor should be (vpopc & 1) != 0. Meaning it's 1 when there is an odd number of set bits.
> Hmm yes I think I've somehow got some wires crossed. Would we assert that vector length is even or does that assumption run deep enough already?
Doesn't (vpopc & 1) != 0 still work for odd VL as long as the vpopc was given the odd VL and only summed VL bits?


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  https://reviews.llvm.org/D100030/new/

https://reviews.llvm.org/D100030