[PATCH] D100035: [RISCV] Add scalable offset under very large stack size.

[Hsiangkai Wang via Phabricator via llvm-commits]

HsiangKai created this revision.
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If the stack size is larger than 12 bits, we have to use a scratch
register to store the stack size. Before we introduce the scalable stack
offset, we could simplify

%0 = ADDI %stack.0, 0

>
=

%scratch = ... # sequence of instructions to move the offset into %scratch
%0 = ADD %fp, %scratch

However, if the offset contains scalable part, we need to consider it.

%0 = ADDI %stack.0, 0

>
=

%scratch = ... # sequence of instructions to move the offset into %scratch
%scratch = ADD %fp, %scratch
%scalable_offset = ... # sequence of instructions for vscaled-offset.
%0 = ADD/SUB %scratch, %scalable_offset


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D100035

Files:
  llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
  llvm/test/CodeGen/RISCV/rvv/addi-scalable-offset.mir


Index: llvm/test/CodeGen/RISCV/rvv/addi-scalable-offset.mir
===================================================================
--- /dev/null
+++ llvm/test/CodeGen/RISCV/rvv/addi-scalable-offset.mir
@@ -0,0 +1,63 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -march=riscv64 -stop-after=prologepilog %s -o - 2>&1 | FileCheck %s
+
+--- |
+  define void @add_scalable_offset(
+            <vscale x 1 x i64> *%pa,
+            i64 %vl)
+  {
+    ret void
+  }
+...
+---
+name: add_scalable_offset
+tracksRegLiveness: true
+frameInfo:
+  isFrameAddressTaken: true
+  stackSize:       2240
+stack:
+  - { id: 0, type: default, offset: 0, size: 1120, alignment: 4,
+      stack-id: default }
+  - { id: 1, type: default, offset: 1120, size: 1120, alignment: 4,
+      stack-id: default }
+  - { id: 2, offset: 0, size: 8, alignment: 8, stack-id: scalable-vector }
+body: |
+  bb.0:
+    liveins: $x10, $x11
+
+    ; CHECK-LABEL: name: add_scalable_offset
+    ; CHECK: liveins: $x10, $x11, $x1
+    ; CHECK: $x2 = frame-setup ADDI $x2, -2032
+    ; CHECK: CFI_INSTRUCTION def_cfa_offset 2032
+    ; CHECK: SD killed $x1, $x2, 2024 :: (store 8 into %stack.3)
+    ; CHECK: SD killed $x8, $x2, 2016 :: (store 8 into %stack.4)
+    ; CHECK: CFI_INSTRUCTION offset $x1, -8
+    ; CHECK: CFI_INSTRUCTION offset $x8, -16
+    ; CHECK: $x8 = frame-setup ADDI $x2, 2032
+    ; CHECK: CFI_INSTRUCTION def_cfa $x8, 0
+    ; CHECK: $x2 = frame-setup ADDI $x2, -240
+    ; CHECK: $x12 = PseudoReadVLENB
+    ; CHECK: $x2 = SUB $x2, killed $x12
+    ; CHECK: dead renamable $x11 = PseudoVSETVLI killed renamable $x11, 88, implicit-def $vl, implicit-def $vtype
+    ; CHECK: renamable $v25 = PseudoVLE64_V_M1 killed renamable $x10, $noreg, 64, implicit $vl, implicit $vtype :: (load unknown-size from %ir.pa, align 8)
+    ; CHECK: $x10 = LUI 1048575
+    ; CHECK: $x10 = ADDIW killed $x10, 1824
+    ; CHECK: $x10 = ADD $x8, killed $x10
+    ; CHECK: $x11 = PseudoReadVLENB
+    ; CHECK: $x10 = SUB killed $x10, killed $x11
+    ; CHECK: VS1R_V killed renamable $v25, killed renamable $x10
+    ; CHECK: $x10 = PseudoReadVLENB
+    ; CHECK: $x2 = ADD $x2, killed $x10
+    ; CHECK: $x2 = frame-destroy ADDI $x2, 240
+    ; CHECK: $x8 = LD $x2, 2016 :: (load 8 from %stack.4)
+    ; CHECK: $x1 = LD $x2, 2024 :: (load 8 from %stack.3)
+    ; CHECK: $x2 = frame-destroy ADDI $x2, 2032
+    ; CHECK: PseudoRET
+    %1:gpr = COPY $x11
+    %0:gpr = COPY $x10
+    %2:vr = PseudoVLE64_V_M1 %0, %1, 64, implicit $vl, implicit $vtype :: (load unknown-size from %ir.pa, align 8)
+    %3:gpr = ADDI %stack.2, 0
+    VS1R_V killed %2:vr, %3:gpr
+    PseudoRET
+
+...
Index: llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
===================================================================
--- llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
+++ llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
@@ -213,7 +213,7 @@
     // Modify Offset and FrameReg appropriately
     Register ScratchReg = MRI.createVirtualRegister(&RISCV::GPRRegClass);
     TII->movImm(MBB, II, DL, ScratchReg, Offset.getFixed());
-    if (MI.getOpcode() == RISCV::ADDI) {
+    if (MI.getOpcode() == RISCV::ADDI && !Offset.getScalable()) {
       BuildMI(MBB, II, DL, TII->get(RISCV::ADD), MI.getOperand(0).getReg())
         .addReg(FrameReg)
         .addReg(ScratchReg, RegState::Kill);
@@ -258,6 +258,13 @@
         TII->getVLENFactoredAmount(MF, MBB, II, ScalableValue);
 
     // 2. Calculate address: FrameReg + result of multiply
+    if (MI.getOpcode() == RISCV::ADDI && !Offset.getFixed()) {
+      BuildMI(MBB, II, DL, TII->get(Opc), MI.getOperand(0).getReg())
+          .addReg(FrameReg, getKillRegState(FrameRegIsKill))
+          .addReg(FactorRegister, RegState::Kill);
+      MI.eraseFromParent();
+      return;
+    }
     Register VL = MRI.createVirtualRegister(&RISCV::GPRRegClass);
     BuildMI(MBB, II, DL, TII->get(Opc), VL)
         .addReg(FrameReg, getKillRegState(FrameRegIsKill))


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