[PATCH] D99906: [PowerPC] Materialize 34-bit constants with pli directly

[Amy Kwan via Phabricator via llvm-commits]

amyk created this revision.
amyk added reviewers: PowerPC, power-llvm-team, stefanp, nemanjai.
amyk added projects: LLVM, PowerPC.
Herald added subscribers: shchenz, hiraditya.
amyk requested review of this revision.

D92879 <https://reviews.llvm.org/D92879> introduced emitting `pli` whenever a constant fits within 34-bits on 64-bit mode.

However, the `pli` instruction is not produced directly. Instead, we materialize
a 34-bit constant in `selectI64Imm()`, and rely on td pattern matching to instead
produce a `pli`. This becomes problematic as there is no guarantee that the 34-bit
constant will reach the td pattern selection for `pli` and it is possible for other
transformations (such as complex bit permutations) to also produce and utilize
the 34-bit constant materialized through `selectI64Imm()`.

This patch instead produces `pli` on Power10 directly whenever the constant fits
within 34-bits.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D99906

Files:
  llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
  llvm/test/CodeGen/PowerPC/p10-constants.ll


Index: llvm/test/CodeGen/PowerPC/p10-constants.ll
===================================================================
--- llvm/test/CodeGen/PowerPC/p10-constants.ll
+++ llvm/test/CodeGen/PowerPC/p10-constants.ll
@@ -303,6 +303,29 @@
   ret i64 1129219040652020412
 }
 
+; Producing `pli` when the constant fits within 34-bits and the constant
+; is being produced in other transformations (such as complex bit permutations).
+define i64 @t_34Bits_Complex(i64 %a, i64 %b) {
+; CHECK-LABEL: t_34Bits_Complex:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    rotldi r4, r4, 30
+; CHECK-NEXT:    rldimi r3, r4, 34, 31
+; CHECK-NEXT:    pli r4, -268435457
+; CHECK-NEXT:    and r3, r3, r4
+; CHECK-NEXT:    blr
+;
+; CHECK32-LABEL: t_34Bits_Complex:
+; CHECK32:       # %bb.0: # %entry
+; CHECK32-NEXT:    rlwinm r4, r6, 0, 4, 2
+; CHECK32-NEXT:    rlwimi r3, r5, 0, 31, 29
+; CHECK32-NEXT:    blr
+entry:
+  %and = and i64 %a, 8589934592
+  %and1 = and i64 %b, -8858370049
+  %or = or i64 %and1, %and
+  ret i64 %or
+}
+
 ; The load immediates resulting from phi-nodes are needed to test whether
 ; li/lis is preferred to pli by the instruction selector.
 define dso_local void @t_phiNode() {
Index: llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
===================================================================
--- llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
+++ llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
@@ -1061,7 +1061,8 @@
   // The pli instruction can materialize up to 34 bits directly.
   // It is defined in the TD file and so we just return the constant.
   if (isInt<34>(Imm))
-    return cast<ConstantSDNode>(CurDAG->getConstant(Imm, dl, MVT::i64));
+    return CurDAG->getMachineNode(PPC::PLI8, dl, MVT::i64,
+                                  CurDAG->getTargetConstant(Imm, dl, MVT::i64));
 
   // Require at least two instructions.
   InstCnt = 2;


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