[PATCH] D99866: [test, AArch64] Fix use of var defined in CHECK-NOT
Thomas Preud'homme via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Sun Apr 4 14:04:27 PDT 2021
thopre created this revision.
thopre added reviewers: kristof.beyls, paquette, aemerson.
Herald added a subscriber: danielkiss.
thopre requested review of this revision.
Herald added a project: LLVM.
LLVM test CodeGen/AArch64/speculation-hardening.ll tries to check for
the absence of a sequence of instructions with several CHECK-NOT with
one of those directives using a variable defined in another. However
CHECK-NOT are checked independently so that is using a variable defined
in a pattern that should not occur in the input.
This commit removes the dependency between those CHECK-NOT by replacing
single occurence of the undefined variable by a regex match, and
multiple occurences by a definition followed by a use.
Repository:
rG LLVM Github Monorepo
https://reviews.llvm.org/D99866
Files:
llvm/test/CodeGen/AArch64/speculation-hardening.ll
Index: llvm/test/CodeGen/AArch64/speculation-hardening.ll
===================================================================
--- llvm/test/CodeGen/AArch64/speculation-hardening.ll
+++ llvm/test/CodeGen/AArch64/speculation-hardening.ll
@@ -16,9 +16,9 @@
; SLH: mov [[TMPREG:x[0-9]+]], sp
; SLH: and [[TMPREG]], [[TMPREG]], x16
; SLH: mov sp, [[TMPREG]]
-; NOSLH-NOT: mov [[TMPREG:x[0-9]+]], sp
-; NOSLH-NOT: and [[TMPREG]], [[TMPREG]], x16
-; NOSLH-NOT: mov sp, [[TMPREG]]
+; NOSLH-NOT: mov {{x[0-9]+}}, sp
+; NOSLH-NOT: and [[TMPREG:x[0-9]+]], [[TMPREG]], x16
+; NOSLH-NOT: mov sp, {{x[0-9]+}}
%call = tail call i32 @tail_callee(i32 %i)
; SLH: cmp sp, #0
; SLH: csetm x16, ne
@@ -45,9 +45,9 @@
; SLH: mov [[TMPREG:x[0-9]+]], sp
; SLH: and [[TMPREG]], [[TMPREG]], x16
; SLH: mov sp, [[TMPREG]]
-; NOSLH-NOT: mov [[TMPREG:x[0-9]+]], sp
-; NOSLH-NOT: and [[TMPREG]], [[TMPREG]], x16
-; NOSLH-NOT: mov sp, [[TMPREG]]
+; NOSLH-NOT: mov {{x[0-9]+}}, sp
+; NOSLH-NOT: and [[TMPREG:x[0-9]+]], [[TMPREG]], x16
+; NOSLH-NOT: mov sp, {{x[0-9]+}}
ret i32 %retval.0
}
@@ -57,9 +57,9 @@
; SLH: mov [[TMPREG:x[0-9]+]], sp
; SLH: and [[TMPREG]], [[TMPREG]], x16
; SLH: mov sp, [[TMPREG]]
-; NOSLH-NOT: mov [[TMPREG:x[0-9]+]], sp
-; NOSLH-NOT: and [[TMPREG]], [[TMPREG]], x16
-; NOSLH-NOT: mov sp, [[TMPREG]]
+; NOSLH-NOT: mov {{x[0-9]+}}, sp
+; NOSLH-NOT: and [[TMPREG:x[0-9]+]], [[TMPREG]], x16
+; NOSLH-NOT: mov sp, {{x[0-9]+}}
; SLH: b tail_callee
; SLH-NOT: cmp sp, #0
%call = tail call i32 @tail_callee(i32 %a)
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