[llvm] a0e611c - [RISCV] Add signext attribute to i32 orc.b test for RV64 to match other Zbb tests.

[Craig Topper via llvm-commits]

Author: Craig Topper
Date: 2021-04-02T16:49:53-07:00
New Revision: a0e611cf722799174fa92116fa8a5c12ff2fa53e

URL: https://github.com/llvm/llvm-project/commit/a0e611cf722799174fa92116fa8a5c12ff2fa53e
DIFF: https://github.com/llvm/llvm-project/commit/a0e611cf722799174fa92116fa8a5c12ff2fa53e.diff

LOG: [RISCV] Add signext attribute to i32 orc.b test for RV64 to match other Zbb tests.

Shows the sext.w at the end that would show up in C code. I'm thinking
orc.b would preserve sign bits from it's input, but I'm not sure.

Added: 
    

Modified: 
    llvm/test/CodeGen/RISCV/rv64zbb-intrinsic.ll

Removed: 
    


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diff  --git a/llvm/test/CodeGen/RISCV/rv64zbb-intrinsic.ll b/llvm/test/CodeGen/RISCV/rv64zbb-intrinsic.ll
index 6f95f043a370..262ed783a32e 100644
--- a/llvm/test/CodeGen/RISCV/rv64zbb-intrinsic.ll
+++ b/llvm/test/CodeGen/RISCV/rv64zbb-intrinsic.ll
@@ -6,15 +6,17 @@
 
 declare i32 @llvm.riscv.orc.b.i32(i32)
 
-define i32 @orcb32(i32 %a) nounwind {
+define signext i32 @orcb32(i32 signext %a) nounwind {
 ; RV64IB-LABEL: orcb32:
 ; RV64IB:       # %bb.0:
 ; RV64IB-NEXT:    orc.b a0, a0
+; RV64IB-NEXT:    sext.w a0, a0
 ; RV64IB-NEXT:    ret
 ;
 ; RV64IBB-LABEL: orcb32:
 ; RV64IBB:       # %bb.0:
 ; RV64IBB-NEXT:    orc.b a0, a0
+; RV64IBB-NEXT:    sext.w a0, a0
 ; RV64IBB-NEXT:    ret
   %tmp = call i32 @llvm.riscv.orc.b.i32(i32 %a)
  ret i32 %tmp