[PATCH] D99667: [RISCV] Add support for bitcasts between scalar and fixed-length vectors

[Fraser Cormack via Phabricator via llvm-commits]

frasercrmck added inline comments.


================
Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:3993
+    }
+    assert(((VT == MVT::i32 && Subtarget.is64Bit() && Subtarget.hasStdExtF()) ||
+            (VT == MVT::i16 && Subtarget.hasStdExtZfh())) &&
----------------
craig.topper wrote:
> This fails for this test case on RV32 with fixed length vectors enabled.
> 
> ```
> define i64 @foo(double %x) {                                                                                                                                                                                                                                                           
>   %a = bitcast double %x to i64                                                                                                                                                                                                                                                        
>   ret i64 %a                                                                                                                                                                                                                                                                           
> }
> ```
Yes of course, that was silly of me. I wish we could be more fine-grained when selecting Custom actions. We can probably just remove the assert and ensure the lines below work correctly, allowing other bitcasts to fall through.


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D99667/new/

https://reviews.llvm.org/D99667