[PATCH] D99667: [RISCV] Add support for bitcasts between scalar and fixed-length vectors

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


================
Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:3993
+    }
+    assert(((VT == MVT::i32 && Subtarget.is64Bit() && Subtarget.hasStdExtF()) ||
+            (VT == MVT::i16 && Subtarget.hasStdExtZfh())) &&
----------------
This fails for this test case on RV32 with fixed length vectors enabled.

```
define i64 @foo(double %x) {                                                                                                                                                                                                                                                           
  %a = bitcast double %x to i64                                                                                                                                                                                                                                                        
  ret i64 %a                                                                                                                                                                                                                                                                           
}
```


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D99667/new/

https://reviews.llvm.org/D99667