[PATCH] D96405: [DAGCombiner] Reduce Shuffle_Vector Nodes Count

[Simon Pilgrim via Phabricator via llvm-commits]

RKSimon added a comment.

In D96405#2658431 <https://reviews.llvm.org/D96405#2658431>, @mmarjieh wrote:

> @RKSimon @craig.topper After investigating and trying out this combine in different DAG combine phases, I noticed that this optimization is not always beneficial for all targets.
> Since this combine is beneficial in our target, I already implemented it in the target specific ISelLowering.
> If we want to continue with this patch and commit it to the community, I suggest that we introduce a target hook for it.

I assume your target is out of tree? Keeping this as a generic combine with a target hook could be fine, assuming the PowerPC team accept the hook being enabled and we retain test coverage.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D96405/new/

https://reviews.llvm.org/D96405