[PATCH] D98670: [RISCV] Pass 'half' in the lower 16 bits of an f32 value when F extension is enabled, but Zfh is not.

Luke Drummond via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Tue Mar 30 03:11:49 PDT 2021


ldrumm added a comment.

In D98670#2649998 <https://reviews.llvm.org/D98670#2649998>, @kito-cheng wrote:

> I just found an issue is unrelated this patch, but related to fp16, RISC-V GCC using the traditional libgcc function name scheme like  `__extendhfdf2`(`__<op><srcT><dstT><N_OP>`) rather than `__gnu_f2h_ieee` (`__gnu_*2*_ieee`).
>
> Function used in GCC:
>
> - `__extendhfsf2` for half -> float
> - `__truncsfhf2` for float -> half
> - `__extendhfdf2` for double -> half
> - `__truncdfhf2` for half -> double

Yes. This was my finding as well. I taught llvm and compiler-rt about them in this patch <https://reviews.llvm.org/D84877> (unmerged). Would this be useful to revisit?


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D98670/new/

https://reviews.llvm.org/D98670



More information about the llvm-commits mailing list