[PATCH] D98670: [RISCV] Pass 'half' in the lower 16 bits of an f32 value when F extension is enabled, but Zfh is not.

Kito Cheng via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Mon Mar 29 18:24:17 PDT 2021

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kito-cheng accepted this revision.
kito-cheng added a comment.
This revision is now accepted and ready to land.

LGTM for NaN-boxing behavior.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D98670/new/

https://reviews.llvm.org/D98670

Previous message: [PATCH] D99557: [RISCV] Move scheduling resources for B into a separate file (NFC)
Next message: [PATCH] D98670: [RISCV] Pass 'half' in the lower 16 bits of an f32 value when F extension is enabled, but Zfh is not.
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