[PATCH] D99418: [AArch64][SVE] Improve codegen for select nodes with fixed types

[Paul Walker via Phabricator via llvm-commits]

paulwalker-arm added inline comments.


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Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:7009
+    SDValue SplatPred = DAG.getNode(ISD::SPLAT_VECTOR, DL, PredVT, SplatVal);
+    return LowerFixedLengthVectorSelectToSVE(
+        DAG.getNode(ISD::VSELECT, DL, Ty, SplatPred, TVal, FVal), DAG);
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Is the call to LowerFixedLengthVectorSelectToSVE strictly necessary?  I would have thought `return DAG.getNode(ISD::VSELECT....` would be sufficient.  We'll then iterate back into the custom lowering code, if required, to lower the VSELECT.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D99418/new/

https://reviews.llvm.org/D99418