[PATCH] D99437: [AArch64] Fix lowering zext/sext of v64i1.

[Florian Hahn via Phabricator via llvm-commits]

fhahn updated this revision to Diff 333934.
fhahn added a comment.



In D99437#2655120 <https://reviews.llvm.org/D99437#2655120>, @dmgreen wrote:

>> I am not sure if you should directly check for `i1` src types, because that would mean we miss other combinations that cause crashes in this function (e.g. `sext <1 x i64> %x to <1 x i128>`) which is caught be the legal type check. Alternatively we could explicitly check for element types that are valid for vectors?
>
> i8 on it's own isn't a legal type, neither is i16.

Yeah, that might be a bit too restrictive. I think the original version (just checking if the MVT is valid/simple) should be enough, because my main concern is avoiding the crash.

> Umm. Do we actually need this code? If so for what?

I added a few additional test cases (a50037aaa6d5 <https://reviews.llvm.org/rGa50037aaa6d5df403ff6b709a367164313ffd23f>) and it appears that while we have a bunch of tests that exercise the code, we get the same code without this combine. I updated the patch to remove it.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D99437/new/

https://reviews.llvm.org/D99437

Files:
  llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
  llvm/test/CodeGen/AArch64/arm64-subvector-extend.ll

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