[PATCH] D99437: [AArch64] Fix lowering zext/sext of v64i1.

Mon Mar 29 01:27:31 PDT 2021

dmgreen added a comment.

> I am not sure if you should directly check for `i1` src types, because that would mean we miss other combinations that cause crashes in this function (e.g. `sext <1 x i64> %x to <1 x i128>`) which is caught be the legal type check. Alternatively we could explicitly check for element types that are valid for vectors?

i8 on it's own isn't a legal type, neither is i16.

Umm. Do we actually need this code? If so for what?

================
Comment at: llvm/test/CodeGen/AArch64/arm64-subvector-extend.ll:192
+; CHECK-NEXT:    sshr.16b v2, v2, #7
+; CHECK-NEXT:    sshr.16b v3, [[V4]], #7
+; CHECK-NEXT:    ret
----------------
This looks odd, with the lanes being interchanged. I presume there's a lot of other code that converts the i1 vector over a call into vectors, and that doesn't preserve the register order?

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D99437/new/

https://reviews.llvm.org/D99437