[PATCH] D99367: [RISCV] When custom iseling masked loads/stores, copy the mask into V0 instead of virtual register.

[Craig Topper via Phabricator via llvm-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rG3dd4aa7d0959: [RISCV] When custom iseling masked loads/stores, copy the mask into V0 instead… (authored by craig.topper).

Changed prior to commit:
  https://reviews.llvm.org/D99367?vs=333481&id=333922#toc

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D99367/new/

https://reviews.llvm.org/D99367

Files:
  llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-load-fp.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-load-int.ll
  llvm/test/CodeGen/RISCV/rvv/mgather-sdnode.ll
  llvm/test/CodeGen/RISCV/rvv/regalloc-fast-crash.ll

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