[PATCH] D98479: [RISCV] Add DAG combine to optimize vXi64 all ones/zeros fixed vector on RV32.

[Craig Topper via Phabricator via llvm-commits]

craig.topper added a comment.

Though we may not having any example tests right now, this pattern can probably also be created by DAG.getConstant after type legalization due to the NodesMustHaveLegalTypes check.


Repository:
  rG LLVM Github Monorepo

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https://reviews.llvm.org/D98479