[PATCH] D98479: [RISCV] Add DAG combine to optimize vXi64 all ones/zeros fixed vector on RV32.

[Fraser Cormack via Phabricator via llvm-commits]

frasercrmck added a comment.

Sorry for putting this off for so long. I do think we need to do something about this. I've tried to think about alternatives with a wider scope (presumably requiring type legalization) but you're right that all-zeroes and all-ones is important. I suppose I'm a bit a paralyzed on what to do.


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D98479/new/

https://reviews.llvm.org/D98479