[PATCH] D98939: [SelectionDAG][AArch64][SVE] Perform SETCC condition legalization in LegalizeVectorOps

[Bradley Smith via Phabricator via llvm-commits]

bsmith added inline comments.


================
Comment at: llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp:1363
+      // condition code, create a new SETCC node.
+      if (Tmp3.getNode())
+        Tmp1 = DAG.getNode(ISD::SETCC, dl, Node->getValueType(0), Tmp1, Tmp2,
----------------
david-arm wrote:
> If it's legal and doesn't need inverting do we even need to reassign Tmp1?
This is for when the operands are swapped, `LegalizeSetCCCondCode` will modify the LHS/RHS input parameters in this case, hence the reassignment is to allow for that.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D98939/new/

https://reviews.llvm.org/D98939