[PATCH] D99324: [AArch64][SVE] Simplify codegen of svdup_lane intrinsic

[Paul Walker via Phabricator via llvm-commits]

paulwalker-arm added a comment.

I'm not saying all the pieces will come for free but this feels like an intrinsic optimisation problem rather than an instruction selection one.  What about extending SVEIntrinsicOpts.cpp to convert the pattern to a stock `splat_vector(extract_vector_elt(vec, idx))` and then letting the code generator decide how best to lower the LLVM way of doing things.  This'll mean we solve the problem once for ACLE and auto-vectorisation.


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D99324/new/

https://reviews.llvm.org/D99324