[PATCH] D99324: [AArch64][SVE] Simplify codegen of svdup_lane intrinsic

[JunMa via Phabricator via llvm-commits]

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For now we generate svdup_lane into sve.dup.x + sve.tbl, however,  the semantics of this intrinsic match the DUP (indexed) instruction if the second input is a constant in the range of that instruction.

This patch adds the pattern match for sve.dup.x + sve.tbl whihc  generate the right version of dup: DUP <Zd>.<T>, <Zn>.<T>[<imm>]


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D99324

Files:
  llvm/lib/Target/AArch64/AArch64InstrFormats.td
  llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
  llvm/lib/Target/AArch64/SVEInstrFormats.td
  llvm/test/CodeGen/AArch64/sve-intrinsics-dup-x.ll
  llvm/test/CodeGen/AArch64/sve-ld-post-inc.ll

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